iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

drm/i915/gvt: Parse default state to update reg whitelist

Browse Source 
Rather than break existing context objects by incorrectly forcing them
to rogue cache coherency and trying to assert a new mapping, read the
reg whitelist from the default context image.

And use gvt->gt, never &dev_priv->gt.

Fixes: 493f30cd086e ("drm/i915/gvt: parse init context to update cmd accessible reg whitelist")
Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Kevin Tian <kevin.tian@intel.com>
Cc: Wang Zhi <zhi.a.wang@intel.com>
Cc: Yan Zhao <yan.y.zhao@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20210129004933.29755-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson 2021-01-29 00:49:32 +00:00 committed by Zhenyu Wang
parent 81ce8f04aa
commit 97ea656521
1 changed files with 20 additions and 73 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

93
drivers/gpu/drm/i915/gvt/cmd_parser.c
View File

@ -41,6 +41,7 @@
#include "gt/intel_lrc.h" #include "gt/intel_lrc.h"
#include "gt/intel_ring.h" #include "gt/intel_ring.h"
#include "gt/intel_gt_requests.h" #include "gt/intel_gt_requests.h"
#include "gt/shmem_utils.h"
#include "gvt.h" #include "gvt.h"
#include "i915_pvinfo.h" #include "i915_pvinfo.h"
#include "trace.h" #include "trace.h"
@ -3094,71 +3095,28 @@ int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
*/ */
void intel_gvt_update_reg_whitelist(struct intel_vgpu *vgpu) void intel_gvt_update_reg_whitelist(struct intel_vgpu *vgpu)
{ {
const unsigned long start = LRC_STATE_PN * PAGE_SIZE;
struct intel_gvt *gvt = vgpu->gvt; struct intel_gvt *gvt = vgpu->gvt;
struct drm_i915_private *dev_priv = gvt->gt->i915;
struct intel_engine_cs *engine; struct intel_engine_cs *engine;
enum intel_engine_id id; enum intel_engine_id id;
const unsigned long start = LRC_STATE_PN * PAGE_SIZE;
struct i915_request *rq;
struct intel_vgpu_submission *s = &vgpu->submission;
struct i915_request *requests[I915_NUM_ENGINES] = {};
bool is_ctx_pinned[I915_NUM_ENGINES] = {};
int ret = 0;
if (gvt->is_reg_whitelist_updated) if (gvt->is_reg_whitelist_updated)
return; return;
for_each_engine(engine, &dev_priv->gt, id) {
ret = intel_context_pin(s->shadow[id]);
if (ret) {
gvt_vgpu_err("fail to pin shadow ctx\n");
goto out;
}
is_ctx_pinned[id] = true;
rq = i915_request_create(s->shadow[id]);
if (IS_ERR(rq)) {
gvt_vgpu_err("fail to alloc default request\n");
ret = -EIO;
goto out;
}
requests[id] = i915_request_get(rq);
i915_request_add(rq);
}
if (intel_gt_wait_for_idle(&dev_priv->gt,
I915_GEM_IDLE_TIMEOUT) == -ETIME) {
ret = -EIO;
goto out;
}
/* scan init ctx to update cmd accessible list */ /* scan init ctx to update cmd accessible list */
for_each_engine(engine, &dev_priv->gt, id) { for_each_engine(engine, gvt->gt, id) {
int size = engine->context_size - PAGE_SIZE;
void *vaddr;
struct parser_exec_state s; struct parser_exec_state s;
struct drm_i915_gem_object *obj; void *vaddr;
struct i915_request *rq; int ret;
rq = requests[id]; if (!engine->default_state)
GEM_BUG_ON(!i915_request_completed(rq)); continue;
GEM_BUG_ON(!intel_context_is_pinned(rq->context));
obj = rq->context->state->obj;
if (!obj) { vaddr = shmem_pin_map(engine->default_state);
ret = -EIO;
goto out;
}
i915_gem_object_set_cache_coherency(obj,
I915_CACHE_LLC);
vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
if (IS_ERR(vaddr)) { if (IS_ERR(vaddr)) {
gvt_err("failed to pin init ctx obj, ring=%d, err=%lx\n", gvt_err("failed to map %s->default state, err:%zd\n",
id, PTR_ERR(vaddr)); engine->name, PTR_ERR(vaddr));
ret = PTR_ERR(vaddr); return;
goto out;
} }
s.buf_type = RING_BUFFER_CTX; s.buf_type = RING_BUFFER_CTX;
@ -3166,9 +3124,9 @@ void intel_gvt_update_reg_whitelist(struct intel_vgpu *vgpu)
s.vgpu = vgpu; s.vgpu = vgpu;
s.engine = engine; s.engine = engine;
s.ring_start = 0; s.ring_start = 0;
s.ring_size = size; s.ring_size = engine->context_size - start;
s.ring_head = 0; s.ring_head = 0;
s.ring_tail = size; s.ring_tail = s.ring_size;
s.rb_va = vaddr + start; s.rb_va = vaddr + start;
s.workload = NULL; s.workload = NULL;
s.is_ctx_wa = false; s.is_ctx_wa = false;
@ -3176,29 +3134,18 @@ void intel_gvt_update_reg_whitelist(struct intel_vgpu *vgpu)
/* skipping the first RING_CTX_SIZE(0x50) dwords */ /* skipping the first RING_CTX_SIZE(0x50) dwords */
ret = ip_gma_set(&s, RING_CTX_SIZE); ret = ip_gma_set(&s, RING_CTX_SIZE);
if (ret) { if (ret == 0) {
i915_gem_object_unpin_map(obj); ret = command_scan(&s, 0, s.ring_size, 0, s.ring_size);
goto out; if (ret)
gvt_err("Scan init ctx error\n");
} }
ret = command_scan(&s, 0, size, 0, size); shmem_unpin_map(engine->default_state, vaddr);
if (ret) if (ret)
gvt_err("Scan init ctx error\n"); return;
i915_gem_object_unpin_map(obj);
} }
out: gvt->is_reg_whitelist_updated = true;
if (!ret)
gvt->is_reg_whitelist_updated = true;
for (id = 0; id < I915_NUM_ENGINES ; id++) {
if (requests[id])
i915_request_put(requests[id]);
if (is_ctx_pinned[id])
intel_context_unpin(s->shadow[id]);
}
} }
int intel_gvt_scan_engine_context(struct intel_vgpu_workload *workload) int intel_gvt_scan_engine_context(struct intel_vgpu_workload *workload)