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drm/amd/display: Set FixRate bit in VSIF V3

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[Why]
Signal FreeSync display that we are in Fixed Rate mode, and
expand the FreeSync range to 1024.

[How]
Set the new bit in SB16:bit0, and augment the min and max
refresh rate with 2 extra bits.

Signed-off-by: AMD\ramini <Reza.Amini@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
AMD\ramini 2020-11-24 17:08:44 -05:00 committed by Alex Deucher
parent 9bc4162665
commit 983bcb4cbe
1 changed files with 8 additions and 4 deletions
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12
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
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@ -610,6 +610,7 @@ static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr,
min_programmed = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? fixed_refresh :
(vrr->state == VRR_STATE_ACTIVE_VARIABLE) ? min_refresh :
(vrr->state == VRR_STATE_INACTIVE) ? min_refresh :
max_refresh; // Non-fs case, program nominal range
max_programmed = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? fixed_refresh :
@ -622,11 +623,14 @@ static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr,
/* PB8 = FreeSync Maximum refresh rate (Hz) */
infopacket->sb[8] = max_programmed & 0xFF;
/* PB11 : MSB FreeSync Minimum refresh rate [Hz] - bits 15:8 */
infopacket->sb[11] = (min_programmed >> 8) & 0xFF;
/* PB11 : MSB FreeSync Minimum refresh rate [Hz] - bits 9:8 */
infopacket->sb[11] = (min_programmed >> 8) & 0x03;
/* PB12 : MSB FreeSync Maximum refresh rate [Hz] - bits 15:8 */
infopacket->sb[12] = (max_programmed >> 8) & 0xFF;
/* PB12 : MSB FreeSync Maximum refresh rate [Hz] - bits 9:8 */
infopacket->sb[12] = (max_programmed >> 8) & 0x03;
/* PB16 : Reserved bits 7:1, FixedRate bit 0 */
infopacket->sb[16] = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? 1 : 0;
//FreeSync HDR
infopacket->sb[9] = 0;