Revert "drm/amd/display: Hande writeback request from userspace"
This reverts commit cd1a4bc22821eea9a98f1beddd1a8d789989a720. [WHY & HOW] The writeback series cause a regression in thunderbolt display. Signed-off-by: Alex Hung <alex.hung@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -416,9 +416,6 @@ struct amdgpu_crtc {
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int otg_inst;
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struct drm_pending_vblank_event *event;
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bool wb_pending;
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struct drm_writeback_connector *wb_conn;
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};
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struct amdgpu_encoder_atom_dig {
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@ -575,7 +575,6 @@ static void dm_crtc_high_irq(void *interrupt_params)
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{
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struct common_irq_params *irq_params = interrupt_params;
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struct amdgpu_device *adev = irq_params->adev;
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struct drm_writeback_job *job;
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struct amdgpu_crtc *acrtc;
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unsigned long flags;
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int vrr_active;
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@ -584,21 +583,6 @@ static void dm_crtc_high_irq(void *interrupt_params)
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if (!acrtc)
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return;
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if (acrtc->wb_pending) {
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if (acrtc->wb_conn) {
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spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags);
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job = list_first_entry_or_null(&acrtc->wb_conn->job_queue,
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struct drm_writeback_job,
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list_entry);
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spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags);
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if (job)
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drm_writeback_signal_completion(acrtc->wb_conn, 0);
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} else
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DRM_ERROR("%s: no amdgpu_crtc wb_conn\n", __func__);
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acrtc->wb_pending = false;
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}
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vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
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drm_dbg_vbl(adev_to_drm(adev),
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@ -8638,12 +8622,6 @@ static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_stat
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stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
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}
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static void dm_clear_writeback(struct amdgpu_display_manager *dm,
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struct dm_crtc_state *crtc_state)
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{
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dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0);
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}
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static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
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struct dc_state *dc_state)
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{
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@ -8653,34 +8631,9 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
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struct drm_crtc *crtc;
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struct drm_crtc_state *old_crtc_state, *new_crtc_state;
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struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
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struct drm_connector_state *old_con_state;
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struct drm_connector *connector;
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bool mode_set_reset_required = false;
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u32 i;
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/* Disable writeback */
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for_each_old_connector_in_state(state, connector, old_con_state, i) {
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struct dm_connector_state *dm_old_con_state;
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struct amdgpu_crtc *acrtc;
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if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
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continue;
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old_crtc_state = NULL;
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dm_old_con_state = to_dm_connector_state(old_con_state);
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if (!dm_old_con_state->base.crtc)
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continue;
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acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc);
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if (acrtc)
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old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
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dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
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dm_clear_writeback(dm, dm_old_crtc_state);
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}
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for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
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new_crtc_state, i) {
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
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@ -8817,97 +8770,6 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
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}
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}
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static void dm_set_writeback(struct amdgpu_display_manager *dm,
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struct dm_crtc_state *crtc_state,
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struct drm_connector *connector,
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struct drm_connector_state *new_con_state)
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{
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struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector);
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struct amdgpu_crtc *acrtc;
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struct dc_writeback_info *wb_info;
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struct pipe_ctx *pipe = NULL;
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struct amdgpu_framebuffer *afb;
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int i = 0;
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wb_info = kzalloc(sizeof(*wb_info), GFP_KERNEL);
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if (!wb_info) {
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DRM_ERROR("Failed to allocate wb_info\n");
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return;
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}
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acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc);
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if (!acrtc) {
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DRM_ERROR("no amdgpu_crtc found\n");
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return;
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}
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afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb);
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if (!afb) {
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DRM_ERROR("No amdgpu_framebuffer found\n");
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return;
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}
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for (i = 0; i < MAX_PIPES; i++) {
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if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) {
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pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i];
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break;
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}
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}
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/* fill in wb_info */
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wb_info->wb_enabled = true;
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wb_info->dwb_pipe_inst = 0;
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wb_info->dwb_params.dwbscl_black_color = 0;
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wb_info->dwb_params.hdr_mult = 0x1F000;
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wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS;
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wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13;
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wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC;
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wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC;
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/* width & height from crtc */
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wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay;
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wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay;
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wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay;
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wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay;
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wb_info->dwb_params.cnv_params.crop_en = false;
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wb_info->dwb_params.stereo_params.stereo_enabled = false;
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wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff; // 10 bits
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wb_info->dwb_params.cnv_params.out_min_pix_val = 0;
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wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB;
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wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS;
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wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444;
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wb_info->dwb_params.capture_rate = dwb_capture_rate_0;
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wb_info->dwb_params.scaler_taps.h_taps = 4;
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wb_info->dwb_params.scaler_taps.v_taps = 4;
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wb_info->dwb_params.scaler_taps.h_taps_c = 2;
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wb_info->dwb_params.scaler_taps.v_taps_c = 2;
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wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING;
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wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0];
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wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1];
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for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) {
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wb_info->mcif_buf_params.luma_address[i] = afb->address;
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wb_info->mcif_buf_params.chroma_address[i] = 0;
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}
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wb_info->mcif_buf_params.p_vmid = 1;
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wb_info->mcif_warmup_params.p_vmid = 1;
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wb_info->writeback_source_plane = pipe->plane_state;
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dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info);
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acrtc->wb_pending = true;
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acrtc->wb_conn = wb_conn;
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drm_writeback_queue_job(wb_conn, new_con_state);
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}
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/**
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* amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
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* @state: The atomic state to commit
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@ -9240,27 +9102,6 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank);
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}
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/* Enable writeback */
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for_each_new_connector_in_state(state, connector, new_con_state, i) {
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struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
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if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
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continue;
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if (!new_con_state->writeback_job)
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continue;
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new_crtc_state = NULL;
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if (acrtc)
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new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
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dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
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dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state);
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}
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/* Update audio instances for each connector. */
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amdgpu_dm_commit_audio(dev, state);
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