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arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards

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Add the nodes relevant to PCIe PHY and PCIe support. PCIe is used for the
WiFi interface (Broadcom Limited BCM4358 802.11ac Wireless LAN SoC).

[mszyprow: rewrote commit message, reworked board/generic dts/dtsi split]

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20201029134017.27400-7-m.szyprowski@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Jaehoon Chung 2020-10-29 14:40:17 +01:00 committed by Krzysztof Kozlowski
parent 29a7bb71a8
commit 98c03b6eef
3 changed files with 60 additions and 2 deletions
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2
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
View File

@ -329,7 +329,7 @@
};
pcie_bus: pcie_bus {
samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6";
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
};

24
arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
View File

@ -968,6 +968,25 @@
bus-width = <4>;
};
&pcie {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pcie_bus &pcie_wlanen>;
vdd10-supply = <&ldo6_reg>;
vdd18-supply = <&ldo7_reg>;
assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_PCIE_100_USER>,
<&cmu_top CLK_MOUT_SCLK_PCIE_100>;
assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
<&cmu_top CLK_MOUT_BUS_PLL_USER>;
assigned-clock-rates = <0>, <100000000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
};
&pcie_phy {
status = "okay";
};
&ppmu_d0_general {
status = "okay";
events {
@ -1084,8 +1103,11 @@
pinctrl-names = "default";
pinctrl-0 = <&initial_ese>;
pcie_wlanen: pcie-wlanen {
PIN(INPUT, gpj2-0, UP, FAST_SR4);
};
initial_ese: initial-state {
PIN(INPUT, gpj2-0, DOWN, FAST_SR1);
PIN(INPUT, gpj2-1, DOWN, FAST_SR1);
PIN(INPUT, gpj2-2, DOWN, FAST_SR1);
};

36
arch/arm64/boot/dts/exynos/exynos5433.dtsi
View File

@ -1029,6 +1029,11 @@
reg = <0x145f0000 0x1038>;
};
syscon_fsys: syscon@156f0000 {
compatible = "syscon";
reg = <0x156f0000 0x1044>;
};
gsc_0: video-scaler@13c00000 {
compatible = "samsung,exynos5433-gsc";
reg = <0x13c00000 0x1000>;
@ -1830,6 +1835,37 @@
status = "disabled";
};
};
pcie_phy: pcie-phy@15680000 {
compatible = "samsung,exynos5433-pcie-phy";
reg = <0x15680000 0x1000>;
samsung,pmu-syscon = <&pmu_system_controller>;
samsung,fsys-sysreg = <&syscon_fsys>;
#phy-cells = <0>;
status = "disabled";
};
pcie: pcie@15700000 {
compatible = "samsung,exynos5433-pcie";
reg = <0x15700000 0x1000>, <0x156b0000 0x1000>,
<0x0c000000 0x1000>;
reg-names = "dbi", "elbi", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_fsys CLK_PCIE>,
<&cmu_fsys CLK_PCLK_PCIE_PHY>;
clock-names = "pcie", "pcie_bus";
num-lanes = <1>;
num-viewport = <3>;
bus-range = <0x00 0xff>;
phys = <&pcie_phy>;
ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>,
<0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
status = "disabled";
};
};
timer: timer {