From 98e710a01738cc99fce0830e4949710bb10fd4ee Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 23 Aug 2020 17:47:24 +0300 Subject: [PATCH] ARM: tegra: acer-a500: Use PLLC for WiFi MMC clock parent The default parent for all MMCs is PLLP, which is running at 216 MHz on Tegra20 and 50 MHz clock can't be derived from PLLP. The maximum SDIO clock rate is 50 MHz, but this rate isn't achievable using PLLP. Let's switch the WiFi MMC clock parent to PLLC in order to get true 50 MHz. This patch doesn't fix any problems, it's just a minor improvement. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 9489eedcf0c9..a0b829738e8f 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -736,6 +736,10 @@ #address-cells = <1>; #size-cells = <0>; + assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; + assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + max-frequency = <50000000>; keep-power-in-suspend; bus-width = <4>;