cpufreq arm updates for 5.19-rc1
- Tegra234 cpufreq support (Sumit Gupta). - Mediatek cleanups and enhancements (Wan Jiabing, Rex-BC Chen, and Jia-Wei Chang). -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEx73Crsp7f6M6scA70rkcPK6BEhwFAmKMabYACgkQ0rkcPK6B Ehz/aA//S/UOQPcDA+rTvIhnrNOKPd0Ppios+xWbw5TSuNyJYRK+DWHdjBeKE6oW /kjq9UMub3ju1TLQbkf3QYRl0shdIAhP5/779YOTILvCOw6j2CDgjPls+rNpxUpl Aob/XVkPh/pjjaYUdrvYz/KhduxX/tOowXiVPAxB15+jfm7xA3QFXHh9+m4Amlr8 iFqQSxyJEupw5DG1I/NUgRYX/tXFl38L0jyMCK1po+n5EWFWkRrJAMGc6FWpiy6x UH0zIZ991tYnEk1sIFWOVWf5Nj4XqmsJ9Sz9PqFihlYLMHVHm7W6NnsYKqOx47ba 073r6Jgt5K5/mhtXVpolnRxFBHOtxS48IsQqVmteGrgdbvMCJ5dYDacEbO4QizyH u9AB1Oljn1pwzOear+xEPeqfr4+6iO/LutDeTypNvYVfnjPWYPnPEp6wOeaPD3qJ dOX0T9mywavcJ9gFyhpc2tzRBkSia7spEYw5gDvtCsU0iVPMesdjazQQbmiomQWU v4DaMIk23htG8tqLDXbFenZ29SKZvvTpGXcNF4EAW8DUk3eruIw23Rd9ZmL90q+i yQj49owl7t0O0RapbUlhhkv0nLaanNK20jTopSpQW+okD8bmPpMsiQgfnDDD3qgO lBGSs5wuJfznoUjjNB7UMzkOkLr0UnwwgEL/+xEezFJKeb8sgTA= =DJhA -----END PGP SIGNATURE----- Merge tag 'cpufreq-arm-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm Pull ARM cpufreq updates for 5.19-rc1 from Viresh Kumar: - Tegra234 cpufreq support (Sumit Gupta). - Mediatek cleanups and enhancements (Wan Jiabing, Rex-BC Chen, and Jia-Wei Chang). * tag 'cpufreq-arm-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm: (21 commits) cpufreq: mediatek: Add support for MT8186 cpufreq: mediatek: Link CCI device to CPU dt-bindings: cpufreq: mediatek: Add MediaTek CCI property cpufreq: mediatek: Fix potential deadlock problem in mtk_cpufreq_set_target cpufreq: mediatek: Add opp notification support cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking() cpufreq: mediatek: Move voltage limits to platform data cpufreq: mediatek: Unregister platform device on exit cpufreq: mediatek: Fix NULL pointer dereference in mediatek-cpufreq cpufreq: mediatek: Make sram regulator optional cpufreq: mediatek: Record previous target vproc value cpufreq: mediatek: Replace old_* with pre_* cpufreq: mediatek: Use device print to show logs cpufreq: mediatek: Enable clocks and regulators cpufreq: mediatek: Remove unused headers cpufreq: mediatek: Cleanup variables and error handling in mtk_cpu_dvfs_info_init() cpufreq: mediatek: Use module_init and add module_exit arm64: tegra: add node for tegra234 cpufreq cpufreq: tegra194: Add support for Tegra234 cpufreq: tegra194: add soc data to support multiple soc ...
This commit is contained in:
Rafael J. Wysocki
commit
990247af7c
@ -0,0 +1,52 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: NVIDIA Tegra CPU COMPLEX CLUSTER area device tree bindings
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maintainers:
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- Sumit Gupta <sumitg@nvidia.com>
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- Mikko Perttunen <mperttunen@nvidia.com>
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- Jon Hunter <jonathanh@nvidia.com>
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- Thierry Reding <thierry.reding@gmail.com>
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description: |+
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The Tegra CPU COMPLEX CLUSTER area contains memory-mapped
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registers that initiate CPU frequency/voltage transitions.
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properties:
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$nodename:
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pattern: "ccplex@([0-9a-f]+)$"
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compatible:
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enum:
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- nvidia,tegra186-ccplex-cluster
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- nvidia,tegra234-ccplex-cluster
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reg:
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maxItems: 1
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nvidia,bpmp:
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$ref: '/schemas/types.yaml#/definitions/phandle'
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description: |
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Specifies the BPMP node that needs to be queried to get
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operating point data for all CPUs.
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additionalProperties: false
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required:
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- compatible
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- reg
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- nvidia,bpmp
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- status
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examples:
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- |
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ccplex@e000000 {
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compatible = "nvidia,tegra234-ccplex-cluster";
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reg = <0x0e000000 0x5ffff>;
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nvidia,bpmp = <&bpmp>;
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status = "okay";
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};
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@ -20,6 +20,13 @@ Optional properties:
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Vsram to fit SoC specific needs. When absent, the voltage scaling
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flow is handled by hardware, hence no software "voltage tracking" is
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needed.
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- mediatek,cci:
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Used to confirm the link status between cpufreq and mediatek cci. Because
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cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs.
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To prevent the issue of high frequency and low voltage, we need to use this
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property to make sure mediatek cci is ready.
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For details of mediatek cci, please refer to
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Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
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- #cooling-cells:
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For details, please refer to
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Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
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@ -1258,6 +1258,13 @@
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};
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};
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ccplex@e000000 {
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compatible = "nvidia,tegra234-ccplex-cluster";
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reg = <0x0 0x0e000000 0x0 0x5ffff>;
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nvidia,bpmp = <&bpmp>;
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status = "okay";
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};
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sram@40000000 {
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compatible = "nvidia,tegra234-sysram", "mmio-sram";
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reg = <0x0 0x40000000 0x0 0x80000>;
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@ -8,18 +8,22 @@
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#include <linux/cpu.h>
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#include <linux/cpufreq.h>
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#include <linux/cpumask.h>
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#include <linux/minmax.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include <linux/thermal.h>
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#define MIN_VOLT_SHIFT (100000)
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#define MAX_VOLT_SHIFT (200000)
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#define MAX_VOLT_LIMIT (1150000)
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#define VOLT_TOL (10000)
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struct mtk_cpufreq_platform_data {
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int min_volt_shift;
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int max_volt_shift;
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int proc_max_volt;
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int sram_min_volt;
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int sram_max_volt;
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bool ccifreq_supported;
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};
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/*
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* The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS
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@ -35,6 +39,7 @@
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struct mtk_cpu_dvfs_info {
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struct cpumask cpus;
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struct device *cpu_dev;
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struct device *cci_dev;
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struct regulator *proc_reg;
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struct regulator *sram_reg;
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struct clk *cpu_clk;
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@ -42,8 +47,20 @@ struct mtk_cpu_dvfs_info {
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struct list_head list_head;
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int intermediate_voltage;
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bool need_voltage_tracking;
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int vproc_on_boot;
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int pre_vproc;
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/* Avoid race condition for regulators between notify and policy */
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struct mutex reg_lock;
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struct notifier_block opp_nb;
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unsigned int opp_cpu;
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unsigned long current_freq;
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const struct mtk_cpufreq_platform_data *soc_data;
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int vtrack_max;
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bool ccifreq_bound;
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};
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static struct platform_device *cpufreq_pdev;
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static LIST_HEAD(dvfs_info_list);
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static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu)
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@ -61,142 +78,123 @@ static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu)
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static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
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int new_vproc)
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{
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const struct mtk_cpufreq_platform_data *soc_data = info->soc_data;
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struct regulator *proc_reg = info->proc_reg;
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struct regulator *sram_reg = info->sram_reg;
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int old_vproc, old_vsram, new_vsram, vsram, vproc, ret;
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int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret;
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int retry = info->vtrack_max;
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old_vproc = regulator_get_voltage(proc_reg);
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if (old_vproc < 0) {
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pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc);
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return old_vproc;
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pre_vproc = regulator_get_voltage(proc_reg);
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if (pre_vproc < 0) {
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dev_err(info->cpu_dev,
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"invalid Vproc value: %d\n", pre_vproc);
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return pre_vproc;
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}
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/* Vsram should not exceed the maximum allowed voltage of SoC. */
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new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT);
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if (old_vproc < new_vproc) {
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/*
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* When scaling up voltages, Vsram and Vproc scale up step
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* by step. At each step, set Vsram to (Vproc + 200mV) first,
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* then set Vproc to (Vsram - 100mV).
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* Keep doing it until Vsram and Vproc hit target voltages.
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*/
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do {
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old_vsram = regulator_get_voltage(sram_reg);
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if (old_vsram < 0) {
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pr_err("%s: invalid Vsram value: %d\n",
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__func__, old_vsram);
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return old_vsram;
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}
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old_vproc = regulator_get_voltage(proc_reg);
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if (old_vproc < 0) {
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pr_err("%s: invalid Vproc value: %d\n",
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__func__, old_vproc);
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return old_vproc;
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}
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pre_vsram = regulator_get_voltage(sram_reg);
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if (pre_vsram < 0) {
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dev_err(info->cpu_dev, "invalid Vsram value: %d\n", pre_vsram);
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return pre_vsram;
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}
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vsram = min(new_vsram, old_vproc + MAX_VOLT_SHIFT);
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new_vsram = clamp(new_vproc + soc_data->min_volt_shift,
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soc_data->sram_min_volt, soc_data->sram_max_volt);
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if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
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vsram = MAX_VOLT_LIMIT;
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do {
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if (pre_vproc <= new_vproc) {
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vsram = clamp(pre_vproc + soc_data->max_volt_shift,
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soc_data->sram_min_volt, new_vsram);
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ret = regulator_set_voltage(sram_reg, vsram,
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soc_data->sram_max_volt);
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/*
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* If the target Vsram hits the maximum voltage,
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* try to set the exact voltage value first.
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*/
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ret = regulator_set_voltage(sram_reg, vsram,
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vsram);
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if (ret)
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ret = regulator_set_voltage(sram_reg,
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vsram - VOLT_TOL,
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vsram);
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vproc = new_vproc;
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} else {
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ret = regulator_set_voltage(sram_reg, vsram,
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vsram + VOLT_TOL);
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vproc = vsram - MIN_VOLT_SHIFT;
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}
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if (ret)
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return ret;
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if (vsram == soc_data->sram_max_volt ||
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new_vsram == soc_data->sram_min_volt)
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vproc = new_vproc;
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else
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vproc = vsram - soc_data->min_volt_shift;
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ret = regulator_set_voltage(proc_reg, vproc,
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vproc + VOLT_TOL);
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soc_data->proc_max_volt);
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if (ret) {
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regulator_set_voltage(sram_reg, old_vsram,
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old_vsram);
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regulator_set_voltage(sram_reg, pre_vsram,
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soc_data->sram_max_volt);
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return ret;
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}
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} while (vproc < new_vproc || vsram < new_vsram);
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} else if (old_vproc > new_vproc) {
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/*
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* When scaling down voltages, Vsram and Vproc scale down step
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* by step. At each step, set Vproc to (Vsram - 200mV) first,
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* then set Vproc to (Vproc + 100mV).
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* Keep doing it until Vsram and Vproc hit target voltages.
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*/
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do {
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old_vproc = regulator_get_voltage(proc_reg);
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if (old_vproc < 0) {
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pr_err("%s: invalid Vproc value: %d\n",
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__func__, old_vproc);
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return old_vproc;
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}
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old_vsram = regulator_get_voltage(sram_reg);
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if (old_vsram < 0) {
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pr_err("%s: invalid Vsram value: %d\n",
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__func__, old_vsram);
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return old_vsram;
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}
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vproc = max(new_vproc, old_vsram - MAX_VOLT_SHIFT);
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} else if (pre_vproc > new_vproc) {
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vproc = max(new_vproc,
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pre_vsram - soc_data->max_volt_shift);
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ret = regulator_set_voltage(proc_reg, vproc,
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vproc + VOLT_TOL);
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soc_data->proc_max_volt);
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if (ret)
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return ret;
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if (vproc == new_vproc)
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vsram = new_vsram;
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else
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vsram = max(new_vsram, vproc + MIN_VOLT_SHIFT);
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if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
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vsram = MAX_VOLT_LIMIT;
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/*
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* If the target Vsram hits the maximum voltage,
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* try to set the exact voltage value first.
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*/
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ret = regulator_set_voltage(sram_reg, vsram,
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vsram);
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if (ret)
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ret = regulator_set_voltage(sram_reg,
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vsram - VOLT_TOL,
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vsram);
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} else {
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ret = regulator_set_voltage(sram_reg, vsram,
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vsram + VOLT_TOL);
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}
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vsram = max(new_vsram,
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vproc + soc_data->min_volt_shift);
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ret = regulator_set_voltage(sram_reg, vsram,
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soc_data->sram_max_volt);
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if (ret) {
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regulator_set_voltage(proc_reg, old_vproc,
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old_vproc);
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regulator_set_voltage(proc_reg, pre_vproc,
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soc_data->proc_max_volt);
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return ret;
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}
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} while (vproc > new_vproc + VOLT_TOL ||
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vsram > new_vsram + VOLT_TOL);
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}
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}
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pre_vproc = vproc;
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pre_vsram = vsram;
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|
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if (--retry < 0) {
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dev_err(info->cpu_dev,
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"over loop count, failed to set voltage\n");
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return -EINVAL;
|
||||
}
|
||||
} while (vproc != new_vproc || vsram != new_vsram);
|
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|
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return 0;
|
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}
|
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|
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static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
|
||||
{
|
||||
const struct mtk_cpufreq_platform_data *soc_data = info->soc_data;
|
||||
int ret;
|
||||
|
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if (info->need_voltage_tracking)
|
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return mtk_cpufreq_voltage_tracking(info, vproc);
|
||||
ret = mtk_cpufreq_voltage_tracking(info, vproc);
|
||||
else
|
||||
return regulator_set_voltage(info->proc_reg, vproc,
|
||||
vproc + VOLT_TOL);
|
||||
ret = regulator_set_voltage(info->proc_reg, vproc,
|
||||
soc_data->proc_max_volt);
|
||||
if (!ret)
|
||||
info->pre_vproc = vproc;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static bool is_ccifreq_ready(struct mtk_cpu_dvfs_info *info)
|
||||
{
|
||||
struct device_link *sup_link;
|
||||
|
||||
if (info->ccifreq_bound)
|
||||
return true;
|
||||
|
||||
sup_link = device_link_add(info->cpu_dev, info->cci_dev,
|
||||
DL_FLAG_AUTOREMOVE_CONSUMER);
|
||||
if (!sup_link) {
|
||||
dev_err(info->cpu_dev, "cpu%d: sup_link is NULL\n", info->opp_cpu);
|
||||
return false;
|
||||
}
|
||||
|
||||
if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND)
|
||||
return false;
|
||||
|
||||
info->ccifreq_bound = true;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
|
||||
@ -208,209 +206,334 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
|
||||
struct mtk_cpu_dvfs_info *info = policy->driver_data;
|
||||
struct device *cpu_dev = info->cpu_dev;
|
||||
struct dev_pm_opp *opp;
|
||||
long freq_hz, old_freq_hz;
|
||||
int vproc, old_vproc, inter_vproc, target_vproc, ret;
|
||||
long freq_hz, pre_freq_hz;
|
||||
int vproc, pre_vproc, inter_vproc, target_vproc, ret;
|
||||
|
||||
inter_vproc = info->intermediate_voltage;
|
||||
|
||||
old_freq_hz = clk_get_rate(cpu_clk);
|
||||
old_vproc = regulator_get_voltage(info->proc_reg);
|
||||
if (old_vproc < 0) {
|
||||
pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc);
|
||||
return old_vproc;
|
||||
pre_freq_hz = clk_get_rate(cpu_clk);
|
||||
|
||||
mutex_lock(&info->reg_lock);
|
||||
|
||||
if (unlikely(info->pre_vproc <= 0))
|
||||
pre_vproc = regulator_get_voltage(info->proc_reg);
|
||||
else
|
||||
pre_vproc = info->pre_vproc;
|
||||
|
||||
if (pre_vproc < 0) {
|
||||
dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc);
|
||||
ret = pre_vproc;
|
||||
goto out;
|
||||
}
|
||||
|
||||
freq_hz = freq_table[index].frequency * 1000;
|
||||
|
||||
opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
|
||||
if (IS_ERR(opp)) {
|
||||
pr_err("cpu%d: failed to find OPP for %ld\n",
|
||||
policy->cpu, freq_hz);
|
||||
return PTR_ERR(opp);
|
||||
dev_err(cpu_dev, "cpu%d: failed to find OPP for %ld\n",
|
||||
policy->cpu, freq_hz);
|
||||
ret = PTR_ERR(opp);
|
||||
goto out;
|
||||
}
|
||||
vproc = dev_pm_opp_get_voltage(opp);
|
||||
dev_pm_opp_put(opp);
|
||||
|
||||
/*
|
||||
* If MediaTek cci is supported but is not ready, we will use the value
|
||||
* of max(target cpu voltage, booting voltage) to prevent high freqeuncy
|
||||
* low voltage crash.
|
||||
*/
|
||||
if (info->soc_data->ccifreq_supported && !is_ccifreq_ready(info))
|
||||
vproc = max(vproc, info->vproc_on_boot);
|
||||
|
||||
/*
|
||||
* If the new voltage or the intermediate voltage is higher than the
|
||||
* current voltage, scale up voltage first.
|
||||
*/
|
||||
target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc;
|
||||
if (old_vproc < target_vproc) {
|
||||
target_vproc = max(inter_vproc, vproc);
|
||||
if (pre_vproc <= target_vproc) {
|
||||
ret = mtk_cpufreq_set_voltage(info, target_vproc);
|
||||
if (ret) {
|
||||
pr_err("cpu%d: failed to scale up voltage!\n",
|
||||
policy->cpu);
|
||||
mtk_cpufreq_set_voltage(info, old_vproc);
|
||||
return ret;
|
||||
dev_err(cpu_dev,
|
||||
"cpu%d: failed to scale up voltage!\n", policy->cpu);
|
||||
mtk_cpufreq_set_voltage(info, pre_vproc);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
/* Reparent the CPU clock to intermediate clock. */
|
||||
ret = clk_set_parent(cpu_clk, info->inter_clk);
|
||||
if (ret) {
|
||||
pr_err("cpu%d: failed to re-parent cpu clock!\n",
|
||||
policy->cpu);
|
||||
mtk_cpufreq_set_voltage(info, old_vproc);
|
||||
WARN_ON(1);
|
||||
return ret;
|
||||
dev_err(cpu_dev,
|
||||
"cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
|
||||
mtk_cpufreq_set_voltage(info, pre_vproc);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Set the original PLL to target rate. */
|
||||
ret = clk_set_rate(armpll, freq_hz);
|
||||
if (ret) {
|
||||
pr_err("cpu%d: failed to scale cpu clock rate!\n",
|
||||
policy->cpu);
|
||||
dev_err(cpu_dev,
|
||||
"cpu%d: failed to scale cpu clock rate!\n", policy->cpu);
|
||||
clk_set_parent(cpu_clk, armpll);
|
||||
mtk_cpufreq_set_voltage(info, old_vproc);
|
||||
return ret;
|
||||
mtk_cpufreq_set_voltage(info, pre_vproc);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Set parent of CPU clock back to the original PLL. */
|
||||
ret = clk_set_parent(cpu_clk, armpll);
|
||||
if (ret) {
|
||||
pr_err("cpu%d: failed to re-parent cpu clock!\n",
|
||||
policy->cpu);
|
||||
dev_err(cpu_dev,
|
||||
"cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
|
||||
mtk_cpufreq_set_voltage(info, inter_vproc);
|
||||
WARN_ON(1);
|
||||
return ret;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* If the new voltage is lower than the intermediate voltage or the
|
||||
* original voltage, scale down to the new voltage.
|
||||
*/
|
||||
if (vproc < inter_vproc || vproc < old_vproc) {
|
||||
if (vproc < inter_vproc || vproc < pre_vproc) {
|
||||
ret = mtk_cpufreq_set_voltage(info, vproc);
|
||||
if (ret) {
|
||||
pr_err("cpu%d: failed to scale down voltage!\n",
|
||||
policy->cpu);
|
||||
dev_err(cpu_dev,
|
||||
"cpu%d: failed to scale down voltage!\n", policy->cpu);
|
||||
clk_set_parent(cpu_clk, info->inter_clk);
|
||||
clk_set_rate(armpll, old_freq_hz);
|
||||
clk_set_rate(armpll, pre_freq_hz);
|
||||
clk_set_parent(cpu_clk, armpll);
|
||||
return ret;
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
info->current_freq = freq_hz;
|
||||
|
||||
out:
|
||||
mutex_unlock(&info->reg_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#define DYNAMIC_POWER "dynamic-power-coefficient"
|
||||
|
||||
static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
|
||||
unsigned long event, void *data)
|
||||
{
|
||||
struct dev_pm_opp *opp = data;
|
||||
struct dev_pm_opp *new_opp;
|
||||
struct mtk_cpu_dvfs_info *info;
|
||||
unsigned long freq, volt;
|
||||
struct cpufreq_policy *policy;
|
||||
int ret = 0;
|
||||
|
||||
info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
|
||||
|
||||
if (event == OPP_EVENT_ADJUST_VOLTAGE) {
|
||||
freq = dev_pm_opp_get_freq(opp);
|
||||
|
||||
mutex_lock(&info->reg_lock);
|
||||
if (info->current_freq == freq) {
|
||||
volt = dev_pm_opp_get_voltage(opp);
|
||||
ret = mtk_cpufreq_set_voltage(info, volt);
|
||||
if (ret)
|
||||
dev_err(info->cpu_dev,
|
||||
"failed to scale voltage: %d\n", ret);
|
||||
}
|
||||
mutex_unlock(&info->reg_lock);
|
||||
} else if (event == OPP_EVENT_DISABLE) {
|
||||
freq = dev_pm_opp_get_freq(opp);
|
||||
|
||||
/* case of current opp item is disabled */
|
||||
if (info->current_freq == freq) {
|
||||
freq = 1;
|
||||
new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev,
|
||||
&freq);
|
||||
if (IS_ERR(new_opp)) {
|
||||
dev_err(info->cpu_dev,
|
||||
"all opp items are disabled\n");
|
||||
ret = PTR_ERR(new_opp);
|
||||
return notifier_from_errno(ret);
|
||||
}
|
||||
|
||||
dev_pm_opp_put(new_opp);
|
||||
policy = cpufreq_cpu_get(info->opp_cpu);
|
||||
if (policy) {
|
||||
cpufreq_driver_target(policy, freq / 1000,
|
||||
CPUFREQ_RELATION_L);
|
||||
cpufreq_cpu_put(policy);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return notifier_from_errno(ret);
|
||||
}
|
||||
|
||||
static struct device *of_get_cci(struct device *cpu_dev)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct platform_device *pdev;
|
||||
|
||||
np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0);
|
||||
if (IS_ERR_OR_NULL(np))
|
||||
return NULL;
|
||||
|
||||
pdev = of_find_device_by_node(np);
|
||||
of_node_put(np);
|
||||
if (IS_ERR_OR_NULL(pdev))
|
||||
return NULL;
|
||||
|
||||
return &pdev->dev;
|
||||
}
|
||||
|
||||
static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
|
||||
{
|
||||
struct device *cpu_dev;
|
||||
struct regulator *proc_reg = ERR_PTR(-ENODEV);
|
||||
struct regulator *sram_reg = ERR_PTR(-ENODEV);
|
||||
struct clk *cpu_clk = ERR_PTR(-ENODEV);
|
||||
struct clk *inter_clk = ERR_PTR(-ENODEV);
|
||||
struct dev_pm_opp *opp;
|
||||
unsigned long rate;
|
||||
int ret;
|
||||
|
||||
cpu_dev = get_cpu_device(cpu);
|
||||
if (!cpu_dev) {
|
||||
pr_err("failed to get cpu%d device\n", cpu);
|
||||
dev_err(cpu_dev, "failed to get cpu%d device\n", cpu);
|
||||
return -ENODEV;
|
||||
}
|
||||
info->cpu_dev = cpu_dev;
|
||||
|
||||
cpu_clk = clk_get(cpu_dev, "cpu");
|
||||
if (IS_ERR(cpu_clk)) {
|
||||
if (PTR_ERR(cpu_clk) == -EPROBE_DEFER)
|
||||
pr_warn("cpu clk for cpu%d not ready, retry.\n", cpu);
|
||||
else
|
||||
pr_err("failed to get cpu clk for cpu%d\n", cpu);
|
||||
|
||||
ret = PTR_ERR(cpu_clk);
|
||||
return ret;
|
||||
info->ccifreq_bound = false;
|
||||
if (info->soc_data->ccifreq_supported) {
|
||||
info->cci_dev = of_get_cci(info->cpu_dev);
|
||||
if (IS_ERR_OR_NULL(info->cci_dev)) {
|
||||
ret = PTR_ERR(info->cci_dev);
|
||||
dev_err(cpu_dev, "cpu%d: failed to get cci device\n", cpu);
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
|
||||
inter_clk = clk_get(cpu_dev, "intermediate");
|
||||
if (IS_ERR(inter_clk)) {
|
||||
if (PTR_ERR(inter_clk) == -EPROBE_DEFER)
|
||||
pr_warn("intermediate clk for cpu%d not ready, retry.\n",
|
||||
cpu);
|
||||
else
|
||||
pr_err("failed to get intermediate clk for cpu%d\n",
|
||||
cpu);
|
||||
info->cpu_clk = clk_get(cpu_dev, "cpu");
|
||||
if (IS_ERR(info->cpu_clk)) {
|
||||
ret = PTR_ERR(info->cpu_clk);
|
||||
return dev_err_probe(cpu_dev, ret,
|
||||
"cpu%d: failed to get cpu clk\n", cpu);
|
||||
}
|
||||
|
||||
ret = PTR_ERR(inter_clk);
|
||||
info->inter_clk = clk_get(cpu_dev, "intermediate");
|
||||
if (IS_ERR(info->inter_clk)) {
|
||||
ret = PTR_ERR(info->inter_clk);
|
||||
dev_err_probe(cpu_dev, ret,
|
||||
"cpu%d: failed to get intermediate clk\n", cpu);
|
||||
goto out_free_resources;
|
||||
}
|
||||
|
||||
proc_reg = regulator_get_optional(cpu_dev, "proc");
|
||||
if (IS_ERR(proc_reg)) {
|
||||
if (PTR_ERR(proc_reg) == -EPROBE_DEFER)
|
||||
pr_warn("proc regulator for cpu%d not ready, retry.\n",
|
||||
cpu);
|
||||
else
|
||||
pr_err("failed to get proc regulator for cpu%d\n",
|
||||
cpu);
|
||||
info->proc_reg = regulator_get_optional(cpu_dev, "proc");
|
||||
if (IS_ERR(info->proc_reg)) {
|
||||
ret = PTR_ERR(info->proc_reg);
|
||||
dev_err_probe(cpu_dev, ret,
|
||||
"cpu%d: failed to get proc regulator\n", cpu);
|
||||
goto out_free_resources;
|
||||
}
|
||||
|
||||
ret = PTR_ERR(proc_reg);
|
||||
ret = regulator_enable(info->proc_reg);
|
||||
if (ret) {
|
||||
dev_warn(cpu_dev, "cpu%d: failed to enable vproc\n", cpu);
|
||||
goto out_free_resources;
|
||||
}
|
||||
|
||||
/* Both presence and absence of sram regulator are valid cases. */
|
||||
sram_reg = regulator_get_exclusive(cpu_dev, "sram");
|
||||
info->sram_reg = regulator_get_optional(cpu_dev, "sram");
|
||||
if (IS_ERR(info->sram_reg))
|
||||
info->sram_reg = NULL;
|
||||
else {
|
||||
ret = regulator_enable(info->sram_reg);
|
||||
if (ret) {
|
||||
dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu);
|
||||
goto out_free_resources;
|
||||
}
|
||||
}
|
||||
|
||||
/* Get OPP-sharing information from "operating-points-v2" bindings */
|
||||
ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus);
|
||||
if (ret) {
|
||||
pr_err("failed to get OPP-sharing information for cpu%d\n",
|
||||
cpu);
|
||||
dev_err(cpu_dev,
|
||||
"cpu%d: failed to get OPP-sharing information\n", cpu);
|
||||
goto out_free_resources;
|
||||
}
|
||||
|
||||
ret = dev_pm_opp_of_cpumask_add_table(&info->cpus);
|
||||
if (ret) {
|
||||
pr_warn("no OPP table for cpu%d\n", cpu);
|
||||
dev_warn(cpu_dev, "cpu%d: no OPP table\n", cpu);
|
||||
goto out_free_resources;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(info->cpu_clk);
|
||||
if (ret)
|
||||
goto out_free_opp_table;
|
||||
|
||||
ret = clk_prepare_enable(info->inter_clk);
|
||||
if (ret)
|
||||
goto out_disable_mux_clock;
|
||||
|
||||
if (info->soc_data->ccifreq_supported) {
|
||||
info->vproc_on_boot = regulator_get_voltage(info->proc_reg);
|
||||
if (info->vproc_on_boot < 0) {
|
||||
dev_err(info->cpu_dev,
|
||||
"invalid Vproc value: %d\n", info->vproc_on_boot);
|
||||
goto out_disable_inter_clock;
|
||||
}
|
||||
}
|
||||
|
||||
/* Search a safe voltage for intermediate frequency. */
|
||||
rate = clk_get_rate(inter_clk);
|
||||
rate = clk_get_rate(info->inter_clk);
|
||||
opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
|
||||
if (IS_ERR(opp)) {
|
||||
pr_err("failed to get intermediate opp for cpu%d\n", cpu);
|
||||
dev_err(cpu_dev, "cpu%d: failed to get intermediate opp\n", cpu);
|
||||
ret = PTR_ERR(opp);
|
||||
goto out_free_opp_table;
|
||||
goto out_disable_inter_clock;
|
||||
}
|
||||
info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
|
||||
dev_pm_opp_put(opp);
|
||||
|
||||
info->cpu_dev = cpu_dev;
|
||||
info->proc_reg = proc_reg;
|
||||
info->sram_reg = IS_ERR(sram_reg) ? NULL : sram_reg;
|
||||
info->cpu_clk = cpu_clk;
|
||||
info->inter_clk = inter_clk;
|
||||
mutex_init(&info->reg_lock);
|
||||
info->current_freq = clk_get_rate(info->cpu_clk);
|
||||
|
||||
info->opp_cpu = cpu;
|
||||
info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
|
||||
ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
|
||||
if (ret) {
|
||||
dev_err(cpu_dev, "cpu%d: failed to register opp notifier\n", cpu);
|
||||
goto out_disable_inter_clock;
|
||||
}
|
||||
|
||||
/*
|
||||
* If SRAM regulator is present, software "voltage tracking" is needed
|
||||
* for this CPU power domain.
|
||||
*/
|
||||
info->need_voltage_tracking = !IS_ERR(sram_reg);
|
||||
info->need_voltage_tracking = (info->sram_reg != NULL);
|
||||
|
||||
/*
|
||||
* We assume min voltage is 0 and tracking target voltage using
|
||||
* min_volt_shift for each iteration.
|
||||
* The vtrack_max is 3 times of expeted iteration count.
|
||||
*/
|
||||
info->vtrack_max = 3 * DIV_ROUND_UP(max(info->soc_data->sram_max_volt,
|
||||
info->soc_data->proc_max_volt),
|
||||
info->soc_data->min_volt_shift);
|
||||
|
||||
return 0;
|
||||
|
||||
out_disable_inter_clock:
|
||||
clk_disable_unprepare(info->inter_clk);
|
||||
|
||||
out_disable_mux_clock:
|
||||
clk_disable_unprepare(info->cpu_clk);
|
||||
|
||||
out_free_opp_table:
|
||||
dev_pm_opp_of_cpumask_remove_table(&info->cpus);
|
||||
|
||||
out_free_resources:
|
||||
if (!IS_ERR(proc_reg))
|
||||
regulator_put(proc_reg);
|
||||
if (!IS_ERR(sram_reg))
|
||||
regulator_put(sram_reg);
|
||||
if (!IS_ERR(cpu_clk))
|
||||
clk_put(cpu_clk);
|
||||
if (!IS_ERR(inter_clk))
|
||||
clk_put(inter_clk);
|
||||
if (regulator_is_enabled(info->proc_reg))
|
||||
regulator_disable(info->proc_reg);
|
||||
if (info->sram_reg && regulator_is_enabled(info->sram_reg))
|
||||
regulator_disable(info->sram_reg);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
|
||||
{
|
||||
if (!IS_ERR(info->proc_reg))
|
||||
regulator_put(info->proc_reg);
|
||||
if (!IS_ERR(info->sram_reg))
|
||||
@ -420,7 +543,30 @@ static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
|
||||
if (!IS_ERR(info->inter_clk))
|
||||
clk_put(info->inter_clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
|
||||
{
|
||||
if (!IS_ERR(info->proc_reg)) {
|
||||
regulator_disable(info->proc_reg);
|
||||
regulator_put(info->proc_reg);
|
||||
}
|
||||
if (!IS_ERR(info->sram_reg)) {
|
||||
regulator_disable(info->sram_reg);
|
||||
regulator_put(info->sram_reg);
|
||||
}
|
||||
if (!IS_ERR(info->cpu_clk)) {
|
||||
clk_disable_unprepare(info->cpu_clk);
|
||||
clk_put(info->cpu_clk);
|
||||
}
|
||||
if (!IS_ERR(info->inter_clk)) {
|
||||
clk_disable_unprepare(info->inter_clk);
|
||||
clk_put(info->inter_clk);
|
||||
}
|
||||
|
||||
dev_pm_opp_of_cpumask_remove_table(&info->cpus);
|
||||
dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
|
||||
}
|
||||
|
||||
static int mtk_cpufreq_init(struct cpufreq_policy *policy)
|
||||
@ -432,14 +578,15 @@ static int mtk_cpufreq_init(struct cpufreq_policy *policy)
|
||||
info = mtk_cpu_dvfs_info_lookup(policy->cpu);
|
||||
if (!info) {
|
||||
pr_err("dvfs info for cpu%d is not initialized.\n",
|
||||
policy->cpu);
|
||||
policy->cpu);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table);
|
||||
if (ret) {
|
||||
pr_err("failed to init cpufreq table for cpu%d: %d\n",
|
||||
policy->cpu, ret);
|
||||
dev_err(info->cpu_dev,
|
||||
"failed to init cpufreq table for cpu%d: %d\n",
|
||||
policy->cpu, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -476,9 +623,17 @@ static struct cpufreq_driver mtk_cpufreq_driver = {
|
||||
|
||||
static int mtk_cpufreq_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct mtk_cpufreq_platform_data *data;
|
||||
struct mtk_cpu_dvfs_info *info, *tmp;
|
||||
int cpu, ret;
|
||||
|
||||
data = dev_get_platdata(&pdev->dev);
|
||||
if (!data) {
|
||||
dev_err(&pdev->dev,
|
||||
"failed to get mtk cpufreq platform data\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
for_each_possible_cpu(cpu) {
|
||||
info = mtk_cpu_dvfs_info_lookup(cpu);
|
||||
if (info)
|
||||
@ -490,6 +645,7 @@ static int mtk_cpufreq_probe(struct platform_device *pdev)
|
||||
goto release_dvfs_info_list;
|
||||
}
|
||||
|
||||
info->soc_data = data;
|
||||
ret = mtk_cpu_dvfs_info_init(info, cpu);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev,
|
||||
@ -525,20 +681,47 @@ static struct platform_driver mtk_cpufreq_platdrv = {
|
||||
.probe = mtk_cpufreq_probe,
|
||||
};
|
||||
|
||||
static const struct mtk_cpufreq_platform_data mt2701_platform_data = {
|
||||
.min_volt_shift = 100000,
|
||||
.max_volt_shift = 200000,
|
||||
.proc_max_volt = 1150000,
|
||||
.sram_min_volt = 0,
|
||||
.sram_max_volt = 1150000,
|
||||
.ccifreq_supported = false,
|
||||
};
|
||||
|
||||
static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
|
||||
.min_volt_shift = 100000,
|
||||
.max_volt_shift = 200000,
|
||||
.proc_max_volt = 1150000,
|
||||
.sram_min_volt = 0,
|
||||
.sram_max_volt = 1150000,
|
||||
.ccifreq_supported = true,
|
||||
};
|
||||
|
||||
static const struct mtk_cpufreq_platform_data mt8186_platform_data = {
|
||||
.min_volt_shift = 100000,
|
||||
.max_volt_shift = 250000,
|
||||
.proc_max_volt = 1118750,
|
||||
.sram_min_volt = 850000,
|
||||
.sram_max_volt = 1118750,
|
||||
.ccifreq_supported = true,
|
||||
};
|
||||
|
||||
/* List of machines supported by this driver */
|
||||
static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
|
||||
{ .compatible = "mediatek,mt2701", },
|
||||
{ .compatible = "mediatek,mt2712", },
|
||||
{ .compatible = "mediatek,mt7622", },
|
||||
{ .compatible = "mediatek,mt7623", },
|
||||
{ .compatible = "mediatek,mt8167", },
|
||||
{ .compatible = "mediatek,mt817x", },
|
||||
{ .compatible = "mediatek,mt8173", },
|
||||
{ .compatible = "mediatek,mt8176", },
|
||||
{ .compatible = "mediatek,mt8183", },
|
||||
{ .compatible = "mediatek,mt8365", },
|
||||
{ .compatible = "mediatek,mt8516", },
|
||||
|
||||
{ .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
|
||||
{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
|
||||
{ .compatible = "mediatek,mt7622", .data = &mt2701_platform_data },
|
||||
{ .compatible = "mediatek,mt7623", .data = &mt2701_platform_data },
|
||||
{ .compatible = "mediatek,mt8167", .data = &mt2701_platform_data },
|
||||
{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
|
||||
{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
|
||||
{ .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
|
||||
{ .compatible = "mediatek,mt8183", .data = &mt8183_platform_data },
|
||||
{ .compatible = "mediatek,mt8186", .data = &mt8186_platform_data },
|
||||
{ .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
|
||||
{ .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines);
|
||||
@ -547,7 +730,7 @@ static int __init mtk_cpufreq_driver_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
const struct of_device_id *match;
|
||||
struct platform_device *pdev;
|
||||
const struct mtk_cpufreq_platform_data *data;
|
||||
int err;
|
||||
|
||||
np = of_find_node_by_path("/");
|
||||
@ -560,6 +743,7 @@ static int __init mtk_cpufreq_driver_init(void)
|
||||
pr_debug("Machine is not compatible with mtk-cpufreq\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
data = match->data;
|
||||
|
||||
err = platform_driver_register(&mtk_cpufreq_platdrv);
|
||||
if (err)
|
||||
@ -571,16 +755,24 @@ static int __init mtk_cpufreq_driver_init(void)
|
||||
* and the device registration codes are put here to handle defer
|
||||
* probing.
|
||||
*/
|
||||
pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0);
|
||||
if (IS_ERR(pdev)) {
|
||||
cpufreq_pdev = platform_device_register_data(NULL, "mtk-cpufreq", -1,
|
||||
data, sizeof(*data));
|
||||
if (IS_ERR(cpufreq_pdev)) {
|
||||
pr_err("failed to register mtk-cpufreq platform device\n");
|
||||
platform_driver_unregister(&mtk_cpufreq_platdrv);
|
||||
return PTR_ERR(pdev);
|
||||
return PTR_ERR(cpufreq_pdev);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
device_initcall(mtk_cpufreq_driver_init);
|
||||
module_init(mtk_cpufreq_driver_init)
|
||||
|
||||
static void __exit mtk_cpufreq_driver_exit(void)
|
||||
{
|
||||
platform_device_unregister(cpufreq_pdev);
|
||||
platform_driver_unregister(&mtk_cpufreq_platdrv);
|
||||
}
|
||||
module_exit(mtk_cpufreq_driver_exit)
|
||||
|
||||
MODULE_DESCRIPTION("MediaTek CPUFreq driver");
|
||||
MODULE_AUTHOR("Pi-Cheng Chen <pi-cheng.chen@linaro.org>");
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved
|
||||
* Copyright (c) 2020 - 2022, NVIDIA CORPORATION. All rights reserved
|
||||
*/
|
||||
|
||||
#include <linux/cpu.h>
|
||||
@ -24,6 +24,17 @@
|
||||
#define CPUFREQ_TBL_STEP_HZ (50 * KHZ * KHZ)
|
||||
#define MAX_CNT ~0U
|
||||
|
||||
#define NDIV_MASK 0x1FF
|
||||
|
||||
#define CORE_OFFSET(cpu) (cpu * 8)
|
||||
#define CMU_CLKS_BASE 0x2000
|
||||
#define SCRATCH_FREQ_CORE_REG(data, cpu) (data->regs + CMU_CLKS_BASE + CORE_OFFSET(cpu))
|
||||
|
||||
#define MMCRAB_CLUSTER_BASE(cl) (0x30000 + (cl * 0x10000))
|
||||
#define CLUSTER_ACTMON_BASE(data, cl) \
|
||||
(data->regs + (MMCRAB_CLUSTER_BASE(cl) + data->soc->actmon_cntr_base))
|
||||
#define CORE_ACTMON_CNTR_REG(data, cl, cpu) (CLUSTER_ACTMON_BASE(data, cl) + CORE_OFFSET(cpu))
|
||||
|
||||
/* cpufreq transisition latency */
|
||||
#define TEGRA_CPUFREQ_TRANSITION_LATENCY (300 * 1000) /* unit in nanoseconds */
|
||||
|
||||
@ -35,12 +46,6 @@ enum cluster {
|
||||
MAX_CLUSTERS,
|
||||
};
|
||||
|
||||
struct tegra194_cpufreq_data {
|
||||
void __iomem *regs;
|
||||
size_t num_clusters;
|
||||
struct cpufreq_frequency_table **tables;
|
||||
};
|
||||
|
||||
struct tegra_cpu_ctr {
|
||||
u32 cpu;
|
||||
u32 coreclk_cnt, last_coreclk_cnt;
|
||||
@ -52,13 +57,127 @@ struct read_counters_work {
|
||||
struct tegra_cpu_ctr c;
|
||||
};
|
||||
|
||||
struct tegra_cpufreq_ops {
|
||||
void (*read_counters)(struct tegra_cpu_ctr *c);
|
||||
void (*set_cpu_ndiv)(struct cpufreq_policy *policy, u64 ndiv);
|
||||
void (*get_cpu_cluster_id)(u32 cpu, u32 *cpuid, u32 *clusterid);
|
||||
int (*get_cpu_ndiv)(u32 cpu, u32 cpuid, u32 clusterid, u64 *ndiv);
|
||||
};
|
||||
|
||||
struct tegra_cpufreq_soc {
|
||||
struct tegra_cpufreq_ops *ops;
|
||||
int maxcpus_per_cluster;
|
||||
phys_addr_t actmon_cntr_base;
|
||||
};
|
||||
|
||||
struct tegra194_cpufreq_data {
|
||||
void __iomem *regs;
|
||||
size_t num_clusters;
|
||||
struct cpufreq_frequency_table **tables;
|
||||
const struct tegra_cpufreq_soc *soc;
|
||||
};
|
||||
|
||||
static struct workqueue_struct *read_counters_wq;
|
||||
|
||||
static void get_cpu_cluster(void *cluster)
|
||||
static void tegra_get_cpu_mpidr(void *mpidr)
|
||||
{
|
||||
u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
|
||||
*((u64 *)mpidr) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
|
||||
}
|
||||
|
||||
*((uint32_t *)cluster) = MPIDR_AFFINITY_LEVEL(mpidr, 1);
|
||||
static void tegra234_get_cpu_cluster_id(u32 cpu, u32 *cpuid, u32 *clusterid)
|
||||
{
|
||||
u64 mpidr;
|
||||
|
||||
smp_call_function_single(cpu, tegra_get_cpu_mpidr, &mpidr, true);
|
||||
|
||||
if (cpuid)
|
||||
*cpuid = MPIDR_AFFINITY_LEVEL(mpidr, 1);
|
||||
if (clusterid)
|
||||
*clusterid = MPIDR_AFFINITY_LEVEL(mpidr, 2);
|
||||
}
|
||||
|
||||
static int tegra234_get_cpu_ndiv(u32 cpu, u32 cpuid, u32 clusterid, u64 *ndiv)
|
||||
{
|
||||
struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
|
||||
void __iomem *freq_core_reg;
|
||||
u64 mpidr_id;
|
||||
|
||||
/* use physical id to get address of per core frequency register */
|
||||
mpidr_id = (clusterid * data->soc->maxcpus_per_cluster) + cpuid;
|
||||
freq_core_reg = SCRATCH_FREQ_CORE_REG(data, mpidr_id);
|
||||
|
||||
*ndiv = readl(freq_core_reg) & NDIV_MASK;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tegra234_set_cpu_ndiv(struct cpufreq_policy *policy, u64 ndiv)
|
||||
{
|
||||
struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
|
||||
void __iomem *freq_core_reg;
|
||||
u32 cpu, cpuid, clusterid;
|
||||
u64 mpidr_id;
|
||||
|
||||
for_each_cpu_and(cpu, policy->cpus, cpu_online_mask) {
|
||||
data->soc->ops->get_cpu_cluster_id(cpu, &cpuid, &clusterid);
|
||||
|
||||
/* use physical id to get address of per core frequency register */
|
||||
mpidr_id = (clusterid * data->soc->maxcpus_per_cluster) + cpuid;
|
||||
freq_core_reg = SCRATCH_FREQ_CORE_REG(data, mpidr_id);
|
||||
|
||||
writel(ndiv, freq_core_reg);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* This register provides access to two counter values with a single
|
||||
* 64-bit read. The counter values are used to determine the average
|
||||
* actual frequency a core has run at over a period of time.
|
||||
* [63:32] PLLP counter: Counts at fixed frequency (408 MHz)
|
||||
* [31:0] Core clock counter: Counts on every core clock cycle
|
||||
*/
|
||||
static void tegra234_read_counters(struct tegra_cpu_ctr *c)
|
||||
{
|
||||
struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
|
||||
void __iomem *actmon_reg;
|
||||
u32 cpuid, clusterid;
|
||||
u64 val;
|
||||
|
||||
data->soc->ops->get_cpu_cluster_id(c->cpu, &cpuid, &clusterid);
|
||||
actmon_reg = CORE_ACTMON_CNTR_REG(data, clusterid, cpuid);
|
||||
|
||||
val = readq(actmon_reg);
|
||||
c->last_refclk_cnt = upper_32_bits(val);
|
||||
c->last_coreclk_cnt = lower_32_bits(val);
|
||||
udelay(US_DELAY);
|
||||
val = readq(actmon_reg);
|
||||
c->refclk_cnt = upper_32_bits(val);
|
||||
c->coreclk_cnt = lower_32_bits(val);
|
||||
}
|
||||
|
||||
static struct tegra_cpufreq_ops tegra234_cpufreq_ops = {
|
||||
.read_counters = tegra234_read_counters,
|
||||
.get_cpu_cluster_id = tegra234_get_cpu_cluster_id,
|
||||
.get_cpu_ndiv = tegra234_get_cpu_ndiv,
|
||||
.set_cpu_ndiv = tegra234_set_cpu_ndiv,
|
||||
};
|
||||
|
||||
const struct tegra_cpufreq_soc tegra234_cpufreq_soc = {
|
||||
.ops = &tegra234_cpufreq_ops,
|
||||
.actmon_cntr_base = 0x9000,
|
||||
.maxcpus_per_cluster = 4,
|
||||
};
|
||||
|
||||
static void tegra194_get_cpu_cluster_id(u32 cpu, u32 *cpuid, u32 *clusterid)
|
||||
{
|
||||
u64 mpidr;
|
||||
|
||||
smp_call_function_single(cpu, tegra_get_cpu_mpidr, &mpidr, true);
|
||||
|
||||
if (cpuid)
|
||||
*cpuid = MPIDR_AFFINITY_LEVEL(mpidr, 0);
|
||||
if (clusterid)
|
||||
*clusterid = MPIDR_AFFINITY_LEVEL(mpidr, 1);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -85,11 +204,24 @@ static inline u32 map_ndiv_to_freq(struct mrq_cpu_ndiv_limits_response
|
||||
return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv);
|
||||
}
|
||||
|
||||
static void tegra194_read_counters(struct tegra_cpu_ctr *c)
|
||||
{
|
||||
u64 val;
|
||||
|
||||
val = read_freq_feedback();
|
||||
c->last_refclk_cnt = lower_32_bits(val);
|
||||
c->last_coreclk_cnt = upper_32_bits(val);
|
||||
udelay(US_DELAY);
|
||||
val = read_freq_feedback();
|
||||
c->refclk_cnt = lower_32_bits(val);
|
||||
c->coreclk_cnt = upper_32_bits(val);
|
||||
}
|
||||
|
||||
static void tegra_read_counters(struct work_struct *work)
|
||||
{
|
||||
struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
|
||||
struct read_counters_work *read_counters_work;
|
||||
struct tegra_cpu_ctr *c;
|
||||
u64 val;
|
||||
|
||||
/*
|
||||
* ref_clk_counter(32 bit counter) runs on constant clk,
|
||||
@ -107,13 +239,7 @@ static void tegra_read_counters(struct work_struct *work)
|
||||
work);
|
||||
c = &read_counters_work->c;
|
||||
|
||||
val = read_freq_feedback();
|
||||
c->last_refclk_cnt = lower_32_bits(val);
|
||||
c->last_coreclk_cnt = upper_32_bits(val);
|
||||
udelay(US_DELAY);
|
||||
val = read_freq_feedback();
|
||||
c->refclk_cnt = lower_32_bits(val);
|
||||
c->coreclk_cnt = upper_32_bits(val);
|
||||
data->soc->ops->read_counters(c);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -177,7 +303,7 @@ static unsigned int tegra194_calculate_speed(u32 cpu)
|
||||
return (rate_mhz * KHZ); /* in KHz */
|
||||
}
|
||||
|
||||
static void get_cpu_ndiv(void *ndiv)
|
||||
static void tegra194_get_cpu_ndiv_sysreg(void *ndiv)
|
||||
{
|
||||
u64 ndiv_val;
|
||||
|
||||
@ -186,30 +312,43 @@ static void get_cpu_ndiv(void *ndiv)
|
||||
*(u64 *)ndiv = ndiv_val;
|
||||
}
|
||||
|
||||
static void set_cpu_ndiv(void *data)
|
||||
static int tegra194_get_cpu_ndiv(u32 cpu, u32 cpuid, u32 clusterid, u64 *ndiv)
|
||||
{
|
||||
struct cpufreq_frequency_table *tbl = data;
|
||||
u64 ndiv_val = (u64)tbl->driver_data;
|
||||
int ret;
|
||||
|
||||
ret = smp_call_function_single(cpu, tegra194_get_cpu_ndiv_sysreg, &ndiv, true);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void tegra194_set_cpu_ndiv_sysreg(void *data)
|
||||
{
|
||||
u64 ndiv_val = *(u64 *)data;
|
||||
|
||||
asm volatile("msr s3_0_c15_c0_4, %0" : : "r" (ndiv_val));
|
||||
}
|
||||
|
||||
static void tegra194_set_cpu_ndiv(struct cpufreq_policy *policy, u64 ndiv)
|
||||
{
|
||||
on_each_cpu_mask(policy->cpus, tegra194_set_cpu_ndiv_sysreg, &ndiv, true);
|
||||
}
|
||||
|
||||
static unsigned int tegra194_get_speed(u32 cpu)
|
||||
{
|
||||
struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
|
||||
struct cpufreq_frequency_table *pos;
|
||||
u32 cpuid, clusterid;
|
||||
unsigned int rate;
|
||||
u64 ndiv;
|
||||
int ret;
|
||||
u32 cl;
|
||||
|
||||
smp_call_function_single(cpu, get_cpu_cluster, &cl, true);
|
||||
data->soc->ops->get_cpu_cluster_id(cpu, &cpuid, &clusterid);
|
||||
|
||||
/* reconstruct actual cpu freq using counters */
|
||||
rate = tegra194_calculate_speed(cpu);
|
||||
|
||||
/* get last written ndiv value */
|
||||
ret = smp_call_function_single(cpu, get_cpu_ndiv, &ndiv, true);
|
||||
ret = data->soc->ops->get_cpu_ndiv(cpu, cpuid, clusterid, &ndiv);
|
||||
if (WARN_ON_ONCE(ret))
|
||||
return rate;
|
||||
|
||||
@ -219,7 +358,7 @@ static unsigned int tegra194_get_speed(u32 cpu)
|
||||
* to the last written ndiv value from freq_table. This is
|
||||
* done to return consistent value.
|
||||
*/
|
||||
cpufreq_for_each_valid_entry(pos, data->tables[cl]) {
|
||||
cpufreq_for_each_valid_entry(pos, data->tables[clusterid]) {
|
||||
if (pos->driver_data != ndiv)
|
||||
continue;
|
||||
|
||||
@ -237,19 +376,22 @@ static unsigned int tegra194_get_speed(u32 cpu)
|
||||
static int tegra194_cpufreq_init(struct cpufreq_policy *policy)
|
||||
{
|
||||
struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
|
||||
u32 cpu;
|
||||
u32 cl;
|
||||
int maxcpus_per_cluster = data->soc->maxcpus_per_cluster;
|
||||
u32 start_cpu, cpu;
|
||||
u32 clusterid;
|
||||
|
||||
smp_call_function_single(policy->cpu, get_cpu_cluster, &cl, true);
|
||||
data->soc->ops->get_cpu_cluster_id(policy->cpu, NULL, &clusterid);
|
||||
|
||||
if (cl >= data->num_clusters || !data->tables[cl])
|
||||
if (clusterid >= data->num_clusters || !data->tables[clusterid])
|
||||
return -EINVAL;
|
||||
|
||||
start_cpu = rounddown(policy->cpu, maxcpus_per_cluster);
|
||||
/* set same policy for all cpus in a cluster */
|
||||
for (cpu = (cl * 2); cpu < ((cl + 1) * 2); cpu++)
|
||||
cpumask_set_cpu(cpu, policy->cpus);
|
||||
|
||||
policy->freq_table = data->tables[cl];
|
||||
for (cpu = start_cpu; cpu < (start_cpu + maxcpus_per_cluster); cpu++) {
|
||||
if (cpu_possible(cpu))
|
||||
cpumask_set_cpu(cpu, policy->cpus);
|
||||
}
|
||||
policy->freq_table = data->tables[clusterid];
|
||||
policy->cpuinfo.transition_latency = TEGRA_CPUFREQ_TRANSITION_LATENCY;
|
||||
|
||||
return 0;
|
||||
@ -259,13 +401,14 @@ static int tegra194_cpufreq_set_target(struct cpufreq_policy *policy,
|
||||
unsigned int index)
|
||||
{
|
||||
struct cpufreq_frequency_table *tbl = policy->freq_table + index;
|
||||
struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
|
||||
|
||||
/*
|
||||
* Each core writes frequency in per core register. Then both cores
|
||||
* in a cluster run at same frequency which is the maximum frequency
|
||||
* request out of the values requested by both cores in that cluster.
|
||||
*/
|
||||
on_each_cpu_mask(policy->cpus, set_cpu_ndiv, tbl, true);
|
||||
data->soc->ops->set_cpu_ndiv(policy, (u64)tbl->driver_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -280,6 +423,18 @@ static struct cpufreq_driver tegra194_cpufreq_driver = {
|
||||
.attr = cpufreq_generic_attr,
|
||||
};
|
||||
|
||||
static struct tegra_cpufreq_ops tegra194_cpufreq_ops = {
|
||||
.read_counters = tegra194_read_counters,
|
||||
.get_cpu_cluster_id = tegra194_get_cpu_cluster_id,
|
||||
.get_cpu_ndiv = tegra194_get_cpu_ndiv,
|
||||
.set_cpu_ndiv = tegra194_set_cpu_ndiv,
|
||||
};
|
||||
|
||||
const struct tegra_cpufreq_soc tegra194_cpufreq_soc = {
|
||||
.ops = &tegra194_cpufreq_ops,
|
||||
.maxcpus_per_cluster = 2,
|
||||
};
|
||||
|
||||
static void tegra194_cpufreq_free_resources(void)
|
||||
{
|
||||
destroy_workqueue(read_counters_wq);
|
||||
@ -359,6 +514,7 @@ init_freq_table(struct platform_device *pdev, struct tegra_bpmp *bpmp,
|
||||
|
||||
static int tegra194_cpufreq_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct tegra_cpufreq_soc *soc;
|
||||
struct tegra194_cpufreq_data *data;
|
||||
struct tegra_bpmp *bpmp;
|
||||
int err, i;
|
||||
@ -367,12 +523,28 @@ static int tegra194_cpufreq_probe(struct platform_device *pdev)
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
soc = of_device_get_match_data(&pdev->dev);
|
||||
|
||||
if (soc->ops && soc->maxcpus_per_cluster) {
|
||||
data->soc = soc;
|
||||
} else {
|
||||
dev_err(&pdev->dev, "soc data missing\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
data->num_clusters = MAX_CLUSTERS;
|
||||
data->tables = devm_kcalloc(&pdev->dev, data->num_clusters,
|
||||
sizeof(*data->tables), GFP_KERNEL);
|
||||
if (!data->tables)
|
||||
return -ENOMEM;
|
||||
|
||||
if (soc->actmon_cntr_base) {
|
||||
/* mmio registers are used for frequency request and re-construction */
|
||||
data->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(data->regs))
|
||||
return PTR_ERR(data->regs);
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, data);
|
||||
|
||||
bpmp = tegra_bpmp_get(&pdev->dev);
|
||||
@ -416,10 +588,10 @@ static int tegra194_cpufreq_remove(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
static const struct of_device_id tegra194_cpufreq_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra194-ccplex", },
|
||||
{ .compatible = "nvidia,tegra194-ccplex", .data = &tegra194_cpufreq_soc },
|
||||
{ .compatible = "nvidia,tegra234-ccplex-cluster", .data = &tegra234_cpufreq_soc },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, tegra194_cpufreq_of_match);
|
||||
|
||||
static struct platform_driver tegra194_ccplex_driver = {
|
||||
.driver = {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user