ath9k_hw: Fill descriptor abstrations for AR9003
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Vasanthakumar Thiagarajan
John W. Linville
parent
b622a720b4
commit
994089db03
@ -168,23 +168,169 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
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return true;
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}
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static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads)
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{
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int checksum;
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checksum = ads->info + ads->link
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+ ads->data0 + ads->ctl3
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+ ads->data1 + ads->ctl5
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+ ads->data2 + ads->ctl7
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+ ads->data3 + ads->ctl9;
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return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum;
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}
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static void ar9003_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
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bool is_firstseg, bool is_lastseg,
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const void *ds0, dma_addr_t buf_addr,
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unsigned int qcu)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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unsigned int descid = 0;
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ads->info = (ATHEROS_VENDOR_ID << AR_DescId_S) |
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(1 << AR_TxRxDesc_S) |
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(1 << AR_CtrlStat_S) |
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(qcu << AR_TxQcuNum_S) | 0x17;
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ads->data0 = buf_addr;
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ads->data1 = 0;
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ads->data2 = 0;
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ads->data3 = 0;
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ads->ctl3 = (seglen << AR_BufLen_S);
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ads->ctl3 &= AR_BufLen;
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/* Fill in pointer checksum and descriptor id */
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ads->ctl10 = ar9003_calc_ptr_chksum(ads);
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ads->ctl10 |= (descid << AR_TxDescId_S);
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if (is_firstseg) {
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ads->ctl12 |= (is_lastseg ? 0 : AR_TxMore);
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} else if (is_lastseg) {
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ads->ctl11 = 0;
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ads->ctl12 = 0;
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ads->ctl13 = AR9003TXC_CONST(ds0)->ctl13;
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ads->ctl14 = AR9003TXC_CONST(ds0)->ctl14;
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} else {
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/* XXX Intermediate descriptor in a multi-descriptor frame.*/
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ads->ctl11 = 0;
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ads->ctl12 = AR_TxMore;
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ads->ctl13 = 0;
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ads->ctl14 = 0;
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}
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}
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static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
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struct ath_tx_status *ts)
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{
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struct ar9003_txs *ads;
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ads = &ah->ts_ring[ah->ts_tail];
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if ((ads->status8 & AR_TxDone) == 0)
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return -EINPROGRESS;
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ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
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if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
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(MS(ads->ds_info, AR_TxRxDesc) != 1)) {
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ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
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"Tx Descriptor error %x\n", ads->ds_info);
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memset(ads, 0, sizeof(*ads));
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return -EIO;
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}
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ts->qid = MS(ads->ds_info, AR_TxQcuNum);
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ts->desc_id = MS(ads->status1, AR_TxDescId);
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ts->ts_seqnum = MS(ads->status8, AR_SeqNum);
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ts->ts_tstamp = ads->status4;
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ts->ts_status = 0;
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ts->ts_flags = 0;
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if (ads->status3 & AR_ExcessiveRetries)
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ts->ts_status |= ATH9K_TXERR_XRETRY;
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if (ads->status3 & AR_Filtered)
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ts->ts_status |= ATH9K_TXERR_FILT;
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if (ads->status3 & AR_FIFOUnderrun) {
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ts->ts_status |= ATH9K_TXERR_FIFO;
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ath9k_hw_updatetxtriglevel(ah, true);
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}
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if (ads->status8 & AR_TxOpExceeded)
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ts->ts_status |= ATH9K_TXERR_XTXOP;
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if (ads->status3 & AR_TxTimerExpired)
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ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
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if (ads->status3 & AR_DescCfgErr)
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ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
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if (ads->status3 & AR_TxDataUnderrun) {
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ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
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ath9k_hw_updatetxtriglevel(ah, true);
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}
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if (ads->status3 & AR_TxDelimUnderrun) {
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ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
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ath9k_hw_updatetxtriglevel(ah, true);
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}
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if (ads->status2 & AR_TxBaStatus) {
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ts->ts_flags |= ATH9K_TX_BA;
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ts->ba_low = ads->status5;
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ts->ba_high = ads->status6;
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}
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ts->ts_rateindex = MS(ads->status8, AR_FinalTxIdx);
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ts->ts_rssi = MS(ads->status7, AR_TxRSSICombined);
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ts->ts_rssi_ctl0 = MS(ads->status2, AR_TxRSSIAnt00);
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ts->ts_rssi_ctl1 = MS(ads->status2, AR_TxRSSIAnt01);
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ts->ts_rssi_ctl2 = MS(ads->status2, AR_TxRSSIAnt02);
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ts->ts_rssi_ext0 = MS(ads->status7, AR_TxRSSIAnt10);
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ts->ts_rssi_ext1 = MS(ads->status7, AR_TxRSSIAnt11);
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ts->ts_rssi_ext2 = MS(ads->status7, AR_TxRSSIAnt12);
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ts->ts_shortretry = MS(ads->status3, AR_RTSFailCnt);
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ts->ts_longretry = MS(ads->status3, AR_DataFailCnt);
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ts->ts_virtcol = MS(ads->status3, AR_VirtRetryCnt);
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ts->ts_antenna = 0;
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ts->tid = MS(ads->status8, AR_TxTid);
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memset(ads, 0, sizeof(*ads));
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return 0;
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}
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static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
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u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
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u32 keyIx, enum ath9k_key_type keyType, u32 flags)
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{
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static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
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u32 pktlen, enum ath9k_pkt_type type, u32 txpower,
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u32 keyIx, enum ath9k_key_type keyType, u32 flags)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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txpower += ah->txpower_indexoffset;
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if (txpower > 63)
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txpower = 63;
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ads->ctl11 = (pktlen & AR_FrameLen)
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| (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
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| SM(txpower, AR_XmitPower)
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| (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
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| (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
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| (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
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| (flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0);
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ads->ctl12 =
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(keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
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| SM(type, AR_FrameType)
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| (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
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| (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
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| (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
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ads->ctl17 = SM(keyType, AR_EncrType);
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ads->ctl18 = 0;
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ads->ctl19 = AR_Not_Sounding;
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ads->ctl20 = 0;
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ads->ctl21 = 0;
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ads->ctl22 = 0;
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}
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static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
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@ -194,41 +340,119 @@ static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
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struct ath9k_11n_rate_series series[],
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u32 nseries, u32 flags)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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struct ar9003_txc *last_ads = (struct ar9003_txc *) lastds;
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u_int32_t ctl11;
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if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
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ctl11 = ads->ctl11;
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if (flags & ATH9K_TXDESC_RTSENA) {
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ctl11 &= ~AR_CTSEnable;
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ctl11 |= AR_RTSEnable;
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} else {
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ctl11 &= ~AR_RTSEnable;
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ctl11 |= AR_CTSEnable;
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}
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ads->ctl11 = ctl11;
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} else {
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ads->ctl11 = (ads->ctl11 & ~(AR_RTSEnable | AR_CTSEnable));
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}
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ads->ctl13 = set11nTries(series, 0)
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| set11nTries(series, 1)
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| set11nTries(series, 2)
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| set11nTries(series, 3)
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| (durUpdateEn ? AR_DurUpdateEna : 0)
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| SM(0, AR_BurstDur);
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ads->ctl14 = set11nRate(series, 0)
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| set11nRate(series, 1)
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| set11nRate(series, 2)
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| set11nRate(series, 3);
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ads->ctl15 = set11nPktDurRTSCTS(series, 0)
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| set11nPktDurRTSCTS(series, 1);
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ads->ctl16 = set11nPktDurRTSCTS(series, 2)
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| set11nPktDurRTSCTS(series, 3);
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ads->ctl18 = set11nRateFlags(series, 0)
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| set11nRateFlags(series, 1)
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| set11nRateFlags(series, 2)
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| set11nRateFlags(series, 3)
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| SM(rtsctsRate, AR_RTSCTSRate);
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ads->ctl19 = AR_Not_Sounding;
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last_ads->ctl13 = ads->ctl13;
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last_ads->ctl14 = ads->ctl14;
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}
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static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
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u32 aggrLen)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
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ads->ctl17 &= ~AR_AggrLen;
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ads->ctl17 |= SM(aggrLen, AR_AggrLen);
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}
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static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
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u32 numDelims)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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unsigned int ctl17;
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ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
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/*
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* We use a stack variable to manipulate ctl6 to reduce uncached
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* read modify, modfiy, write.
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*/
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ctl17 = ads->ctl17;
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ctl17 &= ~AR_PadDelim;
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ctl17 |= SM(numDelims, AR_PadDelim);
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ads->ctl17 = ctl17;
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}
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static void ar9003_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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ads->ctl12 |= AR_IsAggr;
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ads->ctl12 &= ~AR_MoreAggr;
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ads->ctl17 &= ~AR_PadDelim;
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}
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static void ar9003_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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ads->ctl12 &= (~AR_IsAggr & ~AR_MoreAggr);
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}
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static void ar9003_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
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u32 burstDuration)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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ads->ctl13 &= ~AR_BurstDur;
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ads->ctl13 |= SM(burstDuration, AR_BurstDur);
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}
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static void ar9003_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
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u32 vmf)
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u32 vmf)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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if (vmf)
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ads->ctl11 |= AR_VirtMoreFrag;
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else
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ads->ctl11 &= ~AR_VirtMoreFrag;
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}
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void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
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@ -20,7 +20,25 @@
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#define AR_DescId 0xffff0000
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#define AR_DescId_S 16
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#define AR_CtrlStat 0x00004000
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#define AR_CtrlStat_S 14
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#define AR_TxRxDesc 0x00008000
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#define AR_TxRxDesc_S 15
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#define AR_TxQcuNum 0x00000f00
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#define AR_TxQcuNum_S 8
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#define AR_BufLen 0x0fff0000
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#define AR_BufLen_S 16
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#define AR_TxDescId 0xffff0000
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#define AR_TxDescId_S 16
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#define AR_TxPtrChkSum 0x0000ffff
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#define AR_TxTid 0xf0000000
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#define AR_TxTid_S 28
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#define AR_LowRxChain 0x00004000
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#define AR_Not_Sounding 0x20000000
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#define MAP_ISR_S2_CST 6
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#define MAP_ISR_S2_GTT 6
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@ -30,6 +48,8 @@
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#define MAP_ISR_S2_DTIM 7
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#define MAP_ISR_S2_TSFOOR 4
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#define AR9003TXC_CONST(_ds) ((const struct ar9003_txc *) _ds)
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struct ar9003_rxs {
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u32 ds_info;
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u32 status1;
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@ -116,7 +116,10 @@ struct ath_tx_status {
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int8_t ts_rssi_ext0;
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int8_t ts_rssi_ext1;
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int8_t ts_rssi_ext2;
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u8 pad[3];
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u8 qid;
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u16 desc_id;
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u8 tid;
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u8 pad[2];
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u32 ba_low;
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u32 ba_high;
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u32 evm0;
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@ -260,7 +263,7 @@ struct ath_desc {
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#define ATH9K_TXDESC_EXT_AND_CTL 0x0080
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#define ATH9K_TXDESC_VMF 0x0100
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#define ATH9K_TXDESC_FRAG_IS_ON 0x0200
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#define ATH9K_TXDESC_CAB 0x0400
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#define ATH9K_TXDESC_LOWRXCHAIN 0x0400
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#define ATH9K_RXDESC_INTREQ 0x0020
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