s390: use control register bit defines
Use control register bit defines instead of plain numbers where possible. Reviewed-by: Alexander Gordeev <agordeev@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
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@ -49,7 +49,7 @@ static void detect_facilities(void)
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{
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if (test_facility(8)) {
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machine.has_edat1 = 1;
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local_ctl_set_bit(0, 23);
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local_ctl_set_bit(0, CR0_EDAT_BIT);
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}
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if (test_facility(78))
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machine.has_edat2 = 1;
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@ -216,7 +216,7 @@ static __init void detect_machine_facilities(void)
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{
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if (test_facility(8)) {
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S390_lowcore.machine_flags |= MACHINE_FLAG_EDAT1;
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system_ctl_set_bit(0, 23);
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system_ctl_set_bit(0, CR0_EDAT_BIT);
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}
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if (test_facility(78))
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S390_lowcore.machine_flags |= MACHINE_FLAG_EDAT2;
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@ -224,13 +224,13 @@ static __init void detect_machine_facilities(void)
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S390_lowcore.machine_flags |= MACHINE_FLAG_IDTE;
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if (test_facility(50) && test_facility(73)) {
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S390_lowcore.machine_flags |= MACHINE_FLAG_TE;
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system_ctl_set_bit(0, 55);
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system_ctl_set_bit(0, CR0_TRANSACTIONAL_EXECUTION_BIT);
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}
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if (test_facility(51))
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S390_lowcore.machine_flags |= MACHINE_FLAG_TLB_LC;
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if (test_facility(129)) {
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S390_lowcore.machine_flags |= MACHINE_FLAG_VX;
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system_ctl_set_bit(0, 17);
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system_ctl_set_bit(0, CR0_VECTOR_BIT);
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}
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if (test_facility(130))
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S390_lowcore.machine_flags |= MACHINE_FLAG_NX;
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@ -240,7 +240,7 @@ static __init void detect_machine_facilities(void)
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/* Enabled signed clock comparator comparisons */
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S390_lowcore.machine_flags |= MACHINE_FLAG_SCC;
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clock_comparator_max = -1ULL >> 1;
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system_ctl_set_bit(0, 53);
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system_ctl_set_bit(0, CR0_CLOCK_COMPARATOR_SIGN_BIT);
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}
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if (IS_ENABLED(CONFIG_PCI) && test_facility(153)) {
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S390_lowcore.machine_flags |= MACHINE_FLAG_PCI_MIO;
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@ -260,7 +260,7 @@ static inline void save_vector_registers(void)
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static inline void setup_low_address_protection(void)
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{
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system_ctl_set_bit(0, 28);
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system_ctl_set_bit(0, CR0_LOW_ADDRESS_PROTECTION_BIT);
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}
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static inline void setup_access_registers(void)
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@ -273,7 +273,7 @@ static inline void setup_access_registers(void)
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static int __init disable_vector_extension(char *str)
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{
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S390_lowcore.machine_flags &= ~MACHINE_FLAG_VX;
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system_ctl_clear_bit(0, 17);
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system_ctl_clear_bit(0, CR0_VECTOR_BIT);
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return 0;
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}
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early_param("novx", disable_vector_extension);
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@ -28,7 +28,7 @@ static int gs_enable(void)
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return -ENOMEM;
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gs_cb->gsd = 25;
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preempt_disable();
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local_ctl_set_bit(2, 4);
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local_ctl_set_bit(2, CR2_GUARDED_STORAGE_BIT);
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load_gs_cb(gs_cb);
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current->thread.gs_cb = gs_cb;
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preempt_enable();
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@ -42,7 +42,7 @@ static int gs_disable(void)
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preempt_disable();
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kfree(current->thread.gs_cb);
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current->thread.gs_cb = NULL;
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local_ctl_clear_bit(2, 4);
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local_ctl_clear_bit(2, CR2_GUARDED_STORAGE_BIT);
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preempt_enable();
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}
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return 0;
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@ -84,7 +84,7 @@ void gs_load_bc_cb(struct pt_regs *regs)
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if (gs_cb) {
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kfree(current->thread.gs_cb);
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current->thread.gs_bc_cb = NULL;
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local_ctl_set_bit(2, 4);
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local_ctl_set_bit(2, CR2_GUARDED_STORAGE_BIT);
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load_gs_cb(gs_cb);
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current->thread.gs_cb = gs_cb;
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}
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@ -2381,7 +2381,7 @@ void s390_reset_system(void)
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set_prefix(0);
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/* Disable lowcore protection */
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local_ctl_clear_bit(0, 28);
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local_ctl_clear_bit(0, CR0_LOW_ADDRESS_PROTECTION_BIT);
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diag_amode31_ops.diag308_reset();
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}
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@ -185,7 +185,7 @@ void s390_handle_mcck(void)
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static int mchchk_wng_posted = 0;
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/* Use single cpu clear, as we cannot handle smp here. */
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local_ctl_clear_bit(14, 24); /* Disable WARNING MCH */
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local_ctl_clear_bit(14, CR14_WARNING_SUBMASK_BIT);
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if (xchg(&mchchk_wng_posted, 1) == 0)
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kill_cad_pid(SIGPWR, 1);
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}
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@ -505,9 +505,9 @@ NOKPROBE_SYMBOL(s390_do_machine_check);
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static int __init machine_check_init(void)
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{
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system_ctl_set_bit(14, 25); /* enable external damage MCH */
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system_ctl_set_bit(14, 27); /* enable system recovery MCH */
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system_ctl_set_bit(14, 24); /* enable warning MCH */
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system_ctl_set_bit(14, CR14_EXTERNAL_DAMAGE_SUBMASK_BIT);
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system_ctl_set_bit(14, CR14_RECOVERY_SUBMASK_BIT);
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system_ctl_set_bit(14, CR14_WARNING_SUBMASK_BIT);
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return 0;
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}
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early_initcall(machine_check_init);
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@ -1193,7 +1193,7 @@ static int __init cpumf_pmu_init(void)
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* Clear bit 15 of cr0 to unauthorize problem-state to
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* extract measurement counters
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*/
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system_ctl_clear_bit(0, 48);
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system_ctl_clear_bit(0, CR0_CPUMF_EXTRACTION_AUTH_BIT);
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/* register handler for measurement-alert interruptions */
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rc = register_external_irq(EXT_IRQ_MEASURE_ALERT,
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@ -265,7 +265,7 @@ static int paicrypt_add(struct perf_event *event, int flags)
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if (++cpump->active_events == 1) {
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ccd = virt_to_phys(cpump->page) | PAI_CRYPTO_KERNEL_OFFSET;
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WRITE_ONCE(S390_lowcore.ccd, ccd);
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local_ctl_set_bit(0, 50);
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local_ctl_set_bit(0, CR0_CRYPTOGRAPHY_COUNTER_BIT);
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}
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cpump->event = event;
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if (flags & PERF_EF_START && !event->attr.sample_period) {
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@ -294,7 +294,7 @@ static void paicrypt_del(struct perf_event *event, int flags)
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/* Only counting needs to read counter */
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paicrypt_stop(event, PERF_EF_UPDATE);
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if (--cpump->active_events == 0) {
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local_ctl_clear_bit(0, 50);
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local_ctl_clear_bit(0, CR0_CRYPTOGRAPHY_COUNTER_BIT);
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WRITE_ONCE(S390_lowcore.ccd, 0);
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}
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}
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@ -339,7 +339,7 @@ static int paiext_add(struct perf_event *event, int flags)
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S390_lowcore.aicd = virt_to_phys(cpump->paiext_cb);
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pcb->acc = virt_to_phys(cpump->area) | 0x1;
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/* Enable CPU instruction lookup for PAIE1 control block */
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local_ctl_set_bit(0, 49);
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local_ctl_set_bit(0, CR0_PAI_EXTENSION_BIT);
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debug_sprintf_event(paiext_dbg, 4, "%s 1508 %llx acc %llx\n",
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__func__, S390_lowcore.aicd, pcb->acc);
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}
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@ -375,7 +375,7 @@ static void paiext_del(struct perf_event *event, int flags)
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}
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if (--cpump->active_events == 0) {
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/* Disable CPU instruction lookup for PAIE1 control block */
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local_ctl_clear_bit(0, 49);
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local_ctl_clear_bit(0, CR0_PAI_EXTENSION_BIT);
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pcb->acc = 0;
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S390_lowcore.aicd = 0;
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debug_sprintf_event(paiext_dbg, 4, "%s 1508 %llx acc %llx\n",
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@ -1114,7 +1114,7 @@ static int s390_gs_cb_set(struct task_struct *target,
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target->thread.gs_cb = data;
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*target->thread.gs_cb = gs_cb;
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if (target == current) {
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local_ctl_set_bit(2, 4);
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local_ctl_set_bit(2, CR2_GUARDED_STORAGE_BIT);
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restore_gs_cb(target->thread.gs_cb);
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}
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preempt_enable();
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@ -173,10 +173,10 @@ void init_cpu_timer(void)
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clockevents_register_device(cd);
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/* Enable clock comparator timer interrupt. */
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local_ctl_set_bit(0, 11);
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local_ctl_set_bit(0, CR0_CLOCK_COMPARATOR_SUBMASK_BIT);
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/* Always allow the timing alert external interrupt. */
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local_ctl_set_bit(0, 4);
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local_ctl_set_bit(0, CR0_ETR_SUBMASK_BIT);
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}
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static void clock_comparator_interrupt(struct ext_code ext_code,
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@ -4918,7 +4918,7 @@ static void sync_regs_fmt2(struct kvm_vcpu *vcpu)
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}
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if (MACHINE_HAS_GS) {
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preempt_disable();
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local_ctl_set_bit(2, 4);
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local_ctl_set_bit(2, CR2_GUARDED_STORAGE_BIT);
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if (current->thread.gs_cb) {
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vcpu->arch.host_gscb = current->thread.gs_cb;
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save_gs_cb(vcpu->arch.host_gscb);
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@ -4995,13 +4995,13 @@ static void store_regs_fmt2(struct kvm_vcpu *vcpu)
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kvm_run->s.regs.diag318 = vcpu->arch.diag318_info.val;
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if (MACHINE_HAS_GS) {
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preempt_disable();
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local_ctl_set_bit(2, 4);
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local_ctl_set_bit(2, CR2_GUARDED_STORAGE_BIT);
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if (vcpu->arch.gs_enabled)
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save_gs_cb(current->thread.gs_cb);
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current->thread.gs_cb = vcpu->arch.host_gscb;
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restore_gs_cb(vcpu->arch.host_gscb);
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if (!vcpu->arch.host_gscb)
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local_ctl_clear_bit(2, 4);
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local_ctl_clear_bit(2, CR2_GUARDED_STORAGE_BIT);
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vcpu->arch.host_gscb = NULL;
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preempt_enable();
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}
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@ -57,7 +57,7 @@ static int handle_gs(struct kvm_vcpu *vcpu)
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if (test_kvm_facility(vcpu->kvm, 133)) {
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VCPU_EVENT(vcpu, 3, "%s", "ENABLE: GS (lazy)");
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preempt_disable();
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local_ctl_set_bit(2, 4);
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local_ctl_set_bit(2, CR2_GUARDED_STORAGE_BIT);
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current->thread.gs_cb = (struct gs_cb *)&vcpu->run->s.regs.gscb;
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restore_gs_cb(current->thread.gs_cb);
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preempt_enable();
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@ -660,7 +660,7 @@ void __init vmem_map_init(void)
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__set_memory_4k(__va(0), RELOC_HIDE(__va(0), ident_map_size));
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}
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if (MACHINE_HAS_NX)
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system_ctl_set_bit(0, 20);
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system_ctl_set_bit(0, CR0_INSTRUCTION_EXEC_PROTECTION_BIT);
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pr_info("Write protected kernel read-only data: %luk\n",
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(unsigned long)(__end_rodata - _stext) >> 10);
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}
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@ -1094,7 +1094,7 @@ static int __init pci_base_init(void)
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if (MACHINE_HAS_PCI_MIO) {
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static_branch_enable(&have_mio);
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system_ctl_set_bit(2, 5);
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system_ctl_set_bit(2, CR2_MIO_ADDRESSING_BIT);
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}
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rc = zpci_debug_init();
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@ -156,7 +156,7 @@ static int __init crw_machine_check_init(void)
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task = kthread_run(crw_collect_info, NULL, "kmcheck");
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if (IS_ERR(task))
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return PTR_ERR(task);
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system_ctl_set_bit(14, 28); /* enable channel report MCH */
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system_ctl_set_bit(14, CR14_CHANNEL_REPORT_SUBMASK_BIT);
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return 0;
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}
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device_initcall(crw_machine_check_init);
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@ -1823,7 +1823,7 @@ static int __init iucv_init(void)
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rc = -EPROTONOSUPPORT;
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goto out;
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}
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system_ctl_set_bit(0, 1);
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system_ctl_set_bit(0, CR0_IUCV_BIT);
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rc = iucv_query_maxconn();
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if (rc)
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goto out_ctl;
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