media: imx: imx7_mipi_csis: Set the CLKSETTLE register field
Set the CLKSETTLE field explicitly, with a value hardcoded to 0. This brings no functional change, but prepares for calculation of the CLKSETTLE value. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Rui Miguel Silva <rmfrfs@gmail.com> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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@ -310,6 +310,7 @@ struct csi_state {
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u32 clk_frequency;
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u32 hs_settle;
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u32 clk_settle;
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struct reset_control *mrst;
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@ -540,11 +541,15 @@ static int mipi_csis_calculate_params(struct csi_state *state)
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/*
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* The HSSETTLE counter value is document in a table, but can also
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* easily be calculated.
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* easily be calculated. Hardcode the CLKSETTLE value to 0 for now
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* (which is documented as corresponding to CSI-2 v0.87 to v1.00) until
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* we figure out how to compute it correctly.
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*/
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state->hs_settle = (lane_rate - 5000000) / 45000000;
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dev_dbg(state->dev, "lane rate %u, Ths_settle %u\n",
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lane_rate, state->hs_settle);
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state->clk_settle = 0;
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dev_dbg(state->dev, "lane rate %u, Tclk_settle %u, Ths_settle %u\n",
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lane_rate, state->clk_settle, state->hs_settle);
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return 0;
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}
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@ -563,7 +568,8 @@ static void mipi_csis_set_params(struct csi_state *state)
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__mipi_csis_set_format(state);
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mipi_csis_write(state, MIPI_CSIS_DPHY_CMN_CTRL,
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MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(state->hs_settle));
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MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(state->hs_settle) |
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MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(state->clk_settle));
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val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET)
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| (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET)
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