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drm/amd/display: remove global optimize seamless boot stream count

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[Why]
In following sequence driver will add counter twice on
same edp stream.
1. Boot into OS.
2. Set timing with edp only.
3. Set timing with edp and external monitor.
4. Set visibility on for edp.

Step 2 and 3 will add seamless boot counter twice and
subtract it once in step 4.

[How]
Remove global counter and calculate it is used.

Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lewis Huang 2021-02-01 11:26:03 +08:00 committed by Alex Deucher
parent 51a192438b
commit 99929cf057
2 changed files with 19 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -163,6 +163,18 @@ static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_li
return count;
}
static int get_seamless_boot_stream_count(struct dc_state *ctx)
{
uint8_t i;
uint8_t seamless_boot_stream_count = 0;
for (i = 0; i < ctx->stream_count; i++)
if (ctx->streams[i]->apply_seamless_boot_optimization)
seamless_boot_stream_count++;
return seamless_boot_stream_count;
}
static bool create_links(
struct dc *dc,
uint32_t num_virtual_links)
@ -970,7 +982,6 @@ struct dc *dc_create(const struct dc_init_data *init_params)
full_pipe_count,
dc->res_pool->stream_enc_count);
dc->optimize_seamless_boot_streams = 0;
dc->caps.max_links = dc->link_count;
dc->caps.max_audios = dc->res_pool->audio_count;
dc->caps.linear_pitch_alignment = 64;
@ -1377,11 +1388,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
dc->hwss.enable_accelerated_mode(dc, context);
}
for (i = 0; i < context->stream_count; i++)
if (context->streams[i]->apply_seamless_boot_optimization)
dc->optimize_seamless_boot_streams++;
if (context->stream_count > dc->optimize_seamless_boot_streams ||
if (context->stream_count > get_seamless_boot_stream_count(context) ||
context->stream_count == 0)
dc->hwss.prepare_bandwidth(dc, context);
@ -1464,7 +1471,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
dc_enable_stereo(dc, context, dc_streams, context->stream_count);
if (context->stream_count > dc->optimize_seamless_boot_streams ||
if (context->stream_count > get_seamless_boot_stream_count(context) ||
context->stream_count == 0) {
/* Must wait for no flips to be pending before doing optimize bw */
wait_for_no_pipes_pending(dc, context);
@ -1578,7 +1585,7 @@ void dc_post_update_surfaces_to_stream(struct dc *dc)
int i;
struct dc_state *context = dc->current_state;
if ((!dc->optimized_required) || dc->optimize_seamless_boot_streams > 0)
if ((!dc->optimized_required) || get_seamless_boot_stream_count(context) > 0)
return;
post_surface_trace(dc);
@ -2400,7 +2407,7 @@ static void commit_planes_do_stream_update(struct dc *dc,
dc->hwss.optimize_bandwidth(dc, dc->current_state);
} else {
if (dc->optimize_seamless_boot_streams == 0)
if (get_seamless_boot_stream_count(context) == 0)
dc->hwss.prepare_bandwidth(dc, dc->current_state);
core_link_enable_stream(dc->current_state, pipe_ctx);
@ -2439,7 +2446,7 @@ static void commit_planes_for_stream(struct dc *dc,
int i, j;
struct pipe_ctx *top_pipe_to_program = NULL;
if (dc->optimize_seamless_boot_streams > 0 && surface_count > 0) {
if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) {
/* Optimize seamless boot flag keeps clocks and watermarks high until
* first flip. After first flip, optimization is required to lower
* bandwidth. Important to note that it is expected UEFI will
@ -2448,9 +2455,8 @@ static void commit_planes_for_stream(struct dc *dc,
*/
if (stream->apply_seamless_boot_optimization) {
stream->apply_seamless_boot_optimization = false;
dc->optimize_seamless_boot_streams--;
if (dc->optimize_seamless_boot_streams == 0)
if (get_seamless_boot_stream_count(context) == 0)
dc->optimized_required = true;
}
}
@ -2460,7 +2466,7 @@ static void commit_planes_for_stream(struct dc *dc,
dc_allow_idle_optimizations(dc, false);
#endif
if (dc->optimize_seamless_boot_streams == 0)
if (get_seamless_boot_stream_count(context) == 0)
dc->hwss.prepare_bandwidth(dc, context);
context_clock_trace(dc, context);

1
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -628,7 +628,6 @@ struct dc {
#endif
/* Require to maintain clocks and bandwidth for UEFI enabled HW */
int optimize_seamless_boot_streams;
/* FBC compressor */
struct compressor *fbc_compressor;