ARM: shmobile: Add r8a7790 CMT00 clock event
Add clock event support for CMT0 timer channel 0 to the r8a7790 SoC code. On most ARM mach-shmobile the CMT is hooked up to a 32KHz clock but on r8a7790 a 31.7KHz clock is instead used. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -47,6 +47,7 @@
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#define CPG_BASE 0xe6150000
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#define CPG_BASE 0xe6150000
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#define CPG_LEN 0x1000
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#define CPG_LEN 0x1000
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#define SMSTPCR1 0xe6150134
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#define SMSTPCR2 0xe6150138
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#define SMSTPCR2 0xe6150138
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#define SMSTPCR3 0xe615013c
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#define SMSTPCR3 0xe615013c
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#define SMSTPCR5 0xe6150144
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#define SMSTPCR5 0xe6150144
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@ -186,6 +187,7 @@ enum {
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MSTP522,
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MSTP522,
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MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
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MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
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MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
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MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
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MSTP124,
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MSTP_NR
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MSTP_NR
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};
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};
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@ -208,6 +210,7 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
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[MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
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[MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
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[MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
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[MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
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[MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
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[MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */
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};
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};
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static struct clk_lookup lookups[] = {
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static struct clk_lookup lookups[] = {
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@ -270,6 +273,7 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
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CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
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CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
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CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
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CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
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CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
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CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
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};
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};
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#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
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#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
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@ -21,9 +21,10 @@
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#include <linux/irq.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/kernel.h>
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#include <linux/of_platform.h>
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#include <linux/of_platform.h>
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#include <linux/serial_sci.h>
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#include <linux/platform_data/gpio-rcar.h>
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#include <linux/platform_data/gpio-rcar.h>
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#include <linux/platform_data/irq-renesas-irqc.h>
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#include <linux/platform_data/irq-renesas-irqc.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_timer.h>
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#include <mach/common.h>
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#include <mach/common.h>
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#include <mach/irqs.h>
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#include <mach/irqs.h>
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#include <mach/r8a7790.h>
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#include <mach/r8a7790.h>
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@ -159,6 +160,25 @@ static struct resource thermal_resources[] __initdata = {
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thermal_resources, \
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thermal_resources, \
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ARRAY_SIZE(thermal_resources))
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ARRAY_SIZE(thermal_resources))
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static struct sh_timer_config cmt00_platform_data = {
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.name = "CMT00",
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.timer_bit = 0,
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.clockevent_rating = 80,
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};
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static struct resource cmt00_resources[] = {
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DEFINE_RES_MEM(0xffca0510, 0x0c),
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DEFINE_RES_MEM(0xffca0500, 0x04),
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DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
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};
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#define r8a7790_register_cmt(idx) \
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platform_device_register_resndata(&platform_bus, "sh_cmt", \
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idx, cmt##idx##_resources, \
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ARRAY_SIZE(cmt##idx##_resources), \
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&cmt##idx##_platform_data, \
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sizeof(struct sh_timer_config))
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void __init r8a7790_add_standard_devices(void)
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void __init r8a7790_add_standard_devices(void)
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{
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{
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r8a7790_register_scif(SCIFA0);
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r8a7790_register_scif(SCIFA0);
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@ -173,6 +193,7 @@ void __init r8a7790_add_standard_devices(void)
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r8a7790_register_scif(HSCIF1);
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r8a7790_register_scif(HSCIF1);
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r8a7790_register_irqc(0);
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r8a7790_register_irqc(0);
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r8a7790_register_thermal();
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r8a7790_register_thermal();
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r8a7790_register_cmt(00);
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}
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}
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void __init r8a7790_timer_init(void)
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void __init r8a7790_timer_init(void)
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