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drm/i915: pass dev_priv explicitly to PIPE_WGC_C21_C20

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Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_WGC_C21_C20 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/af39047d304f8a5c3c7a643f702f66c06ea5d638.1714399071.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula 2024-04-29 17:02:20 +03:00
parent 366ec5a525
commit 9a1f576058
2 changed files with 3 additions and 3 deletions
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4
drivers/gpu/drm/i915/display/intel_color.c
View File

@ -626,7 +626,7 @@ static void vlv_load_wgc_csc(struct intel_crtc *crtc,
intel_de_write_fw(dev_priv, PIPE_WGC_C12(dev_priv, pipe),
csc->coeff[5]);
intel_de_write_fw(dev_priv, PIPE_WGC_C21_C20(pipe),
intel_de_write_fw(dev_priv, PIPE_WGC_C21_C20(dev_priv, pipe),
csc->coeff[7] << 16 | csc->coeff[6]);
intel_de_write_fw(dev_priv, PIPE_WGC_C22(pipe),
csc->coeff[8]);
@ -653,7 +653,7 @@ static void vlv_read_wgc_csc(struct intel_crtc *crtc,
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C12(dev_priv, pipe));
csc->coeff[5] = tmp & 0xffff;
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C21_C20(pipe));
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C21_C20(dev_priv, pipe));
csc->coeff[6] = tmp & 0xffff;
csc->coeff[7] = tmp >> 16;

2
drivers/gpu/drm/i915/display/intel_color_regs.h
View File

@ -260,7 +260,7 @@
#define PIPE_WGC_C02(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C02)
#define PIPE_WGC_C11_C10(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C11_C10)
#define PIPE_WGC_C12(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C12)
#define PIPE_WGC_C21_C20(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C21_C20)
#define PIPE_WGC_C21_C20(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C21_C20)
#define PIPE_WGC_C22(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C22)
/* pipe CSC & degamma/gamma LUTs on CHV */