iommu/vt-d: Move intel_iommu info from struct intel_svm to struct intel_svm_dev
'struct intel_svm' is shared by all devices bound to a give process,
but records only a single pointer to a 'struct intel_iommu'. Consequently,
cache invalidations may only be applied to a single DMAR unit, and are
erroneously skipped for the other devices.
In preparation for fixing this, rework the structures so that the iommu
pointer resides in 'struct intel_svm_dev', allowing 'struct intel_svm'
to track them in its device list.
Fixes: 1c4f88b7f1
("iommu/vt-d: Shared virtual address in scalable mode")
Cc: Lu Baolu <baolu.lu@linux.intel.com>
Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
Cc: Raj Ashok <ashok.raj@intel.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Reported-by: Guo Kaijie <Kaijie.Guo@intel.com>
Reported-by: Xin Zeng <xin.zeng@intel.com>
Signed-off-by: Guo Kaijie <Kaijie.Guo@intel.com>
Signed-off-by: Xin Zeng <xin.zeng@intel.com>
Signed-off-by: Liu Yi L <yi.l.liu@intel.com>
Tested-by: Guo Kaijie <Kaijie.Guo@intel.com>
Cc: stable@vger.kernel.org # v5.0+
Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/1609949037-25291-2-git-send-email-yi.l.liu@intel.com
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
parent
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@ -142,7 +142,7 @@ static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_d
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}
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desc.qw2 = 0;
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desc.qw3 = 0;
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qi_submit_sync(svm->iommu, &desc, 1, 0);
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qi_submit_sync(sdev->iommu, &desc, 1, 0);
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if (sdev->dev_iotlb) {
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desc.qw0 = QI_DEV_EIOTLB_PASID(svm->pasid) |
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@ -166,7 +166,7 @@ static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_d
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}
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desc.qw2 = 0;
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desc.qw3 = 0;
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qi_submit_sync(svm->iommu, &desc, 1, 0);
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qi_submit_sync(sdev->iommu, &desc, 1, 0);
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}
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}
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@ -211,7 +211,7 @@ static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
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*/
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rcu_read_lock();
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list_for_each_entry_rcu(sdev, &svm->devs, list)
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intel_pasid_tear_down_entry(svm->iommu, sdev->dev,
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intel_pasid_tear_down_entry(sdev->iommu, sdev->dev,
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svm->pasid, true);
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rcu_read_unlock();
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@ -364,6 +364,7 @@ int intel_svm_bind_gpasid(struct iommu_domain *domain, struct device *dev,
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}
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sdev->dev = dev;
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sdev->sid = PCI_DEVID(info->bus, info->devfn);
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sdev->iommu = iommu;
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/* Only count users if device has aux domains */
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if (iommu_dev_feature_enabled(dev, IOMMU_DEV_FEAT_AUX))
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@ -548,6 +549,7 @@ intel_svm_bind_mm(struct device *dev, unsigned int flags,
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goto out;
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}
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sdev->dev = dev;
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sdev->iommu = iommu;
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ret = intel_iommu_enable_pasid(iommu, dev);
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if (ret) {
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@ -577,7 +579,6 @@ intel_svm_bind_mm(struct device *dev, unsigned int flags,
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kfree(sdev);
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goto out;
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}
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svm->iommu = iommu;
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if (pasid_max > intel_pasid_max_id)
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pasid_max = intel_pasid_max_id;
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@ -758,6 +758,7 @@ struct intel_svm_dev {
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struct list_head list;
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struct rcu_head rcu;
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struct device *dev;
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struct intel_iommu *iommu;
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struct svm_dev_ops *ops;
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struct iommu_sva sva;
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u32 pasid;
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@ -771,7 +772,6 @@ struct intel_svm {
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struct mmu_notifier notifier;
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struct mm_struct *mm;
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struct intel_iommu *iommu;
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unsigned int flags;
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u32 pasid;
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int gpasid; /* In case that guest PASID is different from host PASID */
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