MIPS: Respect the ISA level in FCSR handling
Define the central place the default FCSR value is set from, initialised in `cpu_probe'. Determine the FCSR mask applied to values written to the register with CTC1 in the full emulation mode and via ptrace(2), according to the ISA level of processor hardware or the writability of bits 31:18 if actual FPU hardware is used. Software may rely on FCSR bits whose functions our emulator does not implement, so it should not allow them to be set or software may get confused. For ptrace(2) it's just sanity. [ralf@linux-mips.org: Fixed double inclusion of <asm/current.h>.] Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9711/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
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232b6ec5df
commit
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@ -49,6 +49,8 @@ struct cpuinfo_mips {
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unsigned int udelay_val;
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unsigned int udelay_val;
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unsigned int processor_id;
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unsigned int processor_id;
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unsigned int fpu_id;
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unsigned int fpu_id;
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unsigned int fpu_csr31;
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unsigned int fpu_msk31;
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unsigned int msa_id;
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unsigned int msa_id;
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unsigned int cputype;
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unsigned int cputype;
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int isa_level;
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int isa_level;
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@ -11,6 +11,9 @@
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#include <linux/fs.h>
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#include <linux/fs.h>
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#include <uapi/linux/elf.h>
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#include <uapi/linux/elf.h>
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#include <asm/cpu-info.h>
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#include <asm/current.h>
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/* ELF header e_flags defines. */
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/* ELF header e_flags defines. */
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/* MIPS architecture level. */
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/* MIPS architecture level. */
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#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */
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#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */
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@ -297,6 +300,8 @@ do { \
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mips_set_personality_fp(state); \
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mips_set_personality_fp(state); \
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\
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\
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current->thread.abi = &mips_abi; \
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current->thread.abi = &mips_abi; \
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\
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current->thread.fpu.fcr31 = current_cpu_data.fpu_csr31; \
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} while (0)
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} while (0)
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#endif /* CONFIG_32BIT */
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#endif /* CONFIG_32BIT */
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@ -356,6 +361,8 @@ do { \
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else \
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else \
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current->thread.abi = &mips_abi; \
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current->thread.abi = &mips_abi; \
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\
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\
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current->thread.fpu.fcr31 = current_cpu_data.fpu_csr31; \
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\
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p = personality(current->personality); \
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p = personality(current->personality); \
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if (p != PER_LINUX32 && p != PER_LINUX) \
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if (p != PER_LINUX32 && p != PER_LINUX) \
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set_personality(PER_LINUX); \
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set_personality(PER_LINUX); \
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@ -30,7 +30,7 @@
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struct sigcontext;
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struct sigcontext;
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struct sigcontext32;
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struct sigcontext32;
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extern void _init_fpu(void);
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extern void _init_fpu(unsigned int);
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extern void _save_fp(struct task_struct *);
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extern void _save_fp(struct task_struct *);
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extern void _restore_fp(struct task_struct *);
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extern void _restore_fp(struct task_struct *);
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@ -182,6 +182,7 @@ static inline void lose_fpu(int save)
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static inline int init_fpu(void)
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static inline int init_fpu(void)
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{
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{
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unsigned int fcr31 = current->thread.fpu.fcr31;
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int ret = 0;
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int ret = 0;
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if (cpu_has_fpu) {
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if (cpu_has_fpu) {
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@ -192,7 +193,7 @@ static inline int init_fpu(void)
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return ret;
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return ret;
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if (!cpu_has_fre) {
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if (!cpu_has_fre) {
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_init_fpu();
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_init_fpu(fcr31);
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return 0;
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return 0;
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}
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}
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@ -206,7 +207,7 @@ static inline int init_fpu(void)
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config5 = clear_c0_config5(MIPS_CONF5_FRE);
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config5 = clear_c0_config5(MIPS_CONF5_FRE);
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enable_fpu_hazard();
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enable_fpu_hazard();
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_init_fpu();
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_init_fpu(fcr31);
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/* Restore FRE */
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/* Restore FRE */
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write_c0_config5(config5);
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write_c0_config5(config5);
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@ -88,8 +88,6 @@ static inline void fpu_emulator_init_fpu(void)
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struct task_struct *t = current;
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struct task_struct *t = current;
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int i;
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int i;
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t->thread.fpu.fcr31 = 0;
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for (i = 0; i < 32; i++)
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for (i = 0; i < 32; i++)
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set_fpr64(&t->thread.fpu.fpr[i], 0, SIGNALLING_NAN);
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set_fpr64(&t->thread.fpu.fpr[i], 0, SIGNALLING_NAN);
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}
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}
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@ -32,6 +32,35 @@
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#include <asm/spram.h>
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#include <asm/spram.h>
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#include <asm/uaccess.h>
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#include <asm/uaccess.h>
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/*
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* Determine the FCSR mask for FPU hardware.
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*/
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static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
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{
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unsigned long sr, mask, fcsr, fcsr0, fcsr1;
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mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
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sr = read_c0_status();
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__enable_fpu(FPU_AS_IS);
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fcsr = read_32bit_cp1_register(CP1_STATUS);
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fcsr0 = fcsr & mask;
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write_32bit_cp1_register(CP1_STATUS, fcsr0);
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fcsr0 = read_32bit_cp1_register(CP1_STATUS);
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fcsr1 = fcsr | ~mask;
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write_32bit_cp1_register(CP1_STATUS, fcsr1);
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fcsr1 = read_32bit_cp1_register(CP1_STATUS);
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write_32bit_cp1_register(CP1_STATUS, fcsr);
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write_c0_status(sr);
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c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
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}
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/*
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/*
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* Set the FIR feature flags for the FPU emulator.
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* Set the FIR feature flags for the FPU emulator.
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*/
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*/
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@ -50,11 +79,15 @@ static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
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c->fpu_id = value;
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c->fpu_id = value;
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}
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}
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/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
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static unsigned int mips_nofpu_msk31;
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static int mips_fpu_disabled;
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static int mips_fpu_disabled;
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static int __init fpu_disable(char *s)
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static int __init fpu_disable(char *s)
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{
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{
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boot_cpu_data.options &= ~MIPS_CPU_FPU;
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boot_cpu_data.options &= ~MIPS_CPU_FPU;
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boot_cpu_data.fpu_msk31 = mips_nofpu_msk31;
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cpu_set_nofpu_id(&boot_cpu_data);
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cpu_set_nofpu_id(&boot_cpu_data);
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mips_fpu_disabled = 1;
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mips_fpu_disabled = 1;
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@ -597,6 +630,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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case PRID_IMP_R2000:
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case PRID_IMP_R2000:
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c->cputype = CPU_R2000;
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c->cputype = CPU_R2000;
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__cpu_name[cpu] = "R2000";
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__cpu_name[cpu] = "R2000";
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c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
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c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
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c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
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MIPS_CPU_NOFPUEX;
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MIPS_CPU_NOFPUEX;
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if (__cpu_has_fpu())
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if (__cpu_has_fpu())
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@ -616,6 +650,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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c->cputype = CPU_R3000;
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c->cputype = CPU_R3000;
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__cpu_name[cpu] = "R3000";
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__cpu_name[cpu] = "R3000";
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}
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}
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c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
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c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
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c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
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MIPS_CPU_NOFPUEX;
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MIPS_CPU_NOFPUEX;
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if (__cpu_has_fpu())
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if (__cpu_has_fpu())
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@ -664,6 +699,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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}
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}
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set_isa(c, MIPS_CPU_ISA_III);
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set_isa(c, MIPS_CPU_ISA_III);
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c->fpu_msk31 |= FPU_CSR_CONDX;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_WATCH | MIPS_CPU_VCE |
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MIPS_CPU_WATCH | MIPS_CPU_VCE |
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MIPS_CPU_LLSC;
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MIPS_CPU_LLSC;
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@ -671,6 +707,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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break;
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break;
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case PRID_IMP_VR41XX:
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case PRID_IMP_VR41XX:
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set_isa(c, MIPS_CPU_ISA_III);
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set_isa(c, MIPS_CPU_ISA_III);
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c->fpu_msk31 |= FPU_CSR_CONDX;
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c->options = R4K_OPTS;
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c->options = R4K_OPTS;
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c->tlbsize = 32;
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c->tlbsize = 32;
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switch (c->processor_id & 0xf0) {
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switch (c->processor_id & 0xf0) {
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@ -712,6 +749,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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c->cputype = CPU_R4300;
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c->cputype = CPU_R4300;
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__cpu_name[cpu] = "R4300";
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__cpu_name[cpu] = "R4300";
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set_isa(c, MIPS_CPU_ISA_III);
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set_isa(c, MIPS_CPU_ISA_III);
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c->fpu_msk31 |= FPU_CSR_CONDX;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_LLSC;
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MIPS_CPU_LLSC;
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c->tlbsize = 32;
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c->tlbsize = 32;
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@ -720,6 +758,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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c->cputype = CPU_R4600;
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c->cputype = CPU_R4600;
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__cpu_name[cpu] = "R4600";
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__cpu_name[cpu] = "R4600";
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set_isa(c, MIPS_CPU_ISA_III);
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set_isa(c, MIPS_CPU_ISA_III);
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c->fpu_msk31 |= FPU_CSR_CONDX;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_LLSC;
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MIPS_CPU_LLSC;
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c->tlbsize = 48;
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c->tlbsize = 48;
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@ -735,11 +774,13 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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c->cputype = CPU_R4650;
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c->cputype = CPU_R4650;
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__cpu_name[cpu] = "R4650";
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__cpu_name[cpu] = "R4650";
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set_isa(c, MIPS_CPU_ISA_III);
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set_isa(c, MIPS_CPU_ISA_III);
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c->fpu_msk31 |= FPU_CSR_CONDX;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
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c->tlbsize = 48;
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c->tlbsize = 48;
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break;
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break;
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#endif
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#endif
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case PRID_IMP_TX39:
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case PRID_IMP_TX39:
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c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
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c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
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c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
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if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
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if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
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@ -765,6 +806,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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c->cputype = CPU_R4700;
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c->cputype = CPU_R4700;
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__cpu_name[cpu] = "R4700";
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__cpu_name[cpu] = "R4700";
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set_isa(c, MIPS_CPU_ISA_III);
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set_isa(c, MIPS_CPU_ISA_III);
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c->fpu_msk31 |= FPU_CSR_CONDX;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_LLSC;
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MIPS_CPU_LLSC;
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c->tlbsize = 48;
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c->tlbsize = 48;
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@ -773,6 +815,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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c->cputype = CPU_TX49XX;
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c->cputype = CPU_TX49XX;
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__cpu_name[cpu] = "R49XX";
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__cpu_name[cpu] = "R49XX";
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set_isa(c, MIPS_CPU_ISA_III);
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set_isa(c, MIPS_CPU_ISA_III);
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c->fpu_msk31 |= FPU_CSR_CONDX;
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c->options = R4K_OPTS | MIPS_CPU_LLSC;
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c->options = R4K_OPTS | MIPS_CPU_LLSC;
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if (!(c->processor_id & 0x08))
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if (!(c->processor_id & 0x08))
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c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
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c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
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@ -814,6 +857,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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c->cputype = CPU_R6000;
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c->cputype = CPU_R6000;
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__cpu_name[cpu] = "R6000";
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__cpu_name[cpu] = "R6000";
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set_isa(c, MIPS_CPU_ISA_II);
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set_isa(c, MIPS_CPU_ISA_II);
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c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
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c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
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c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
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MIPS_CPU_LLSC;
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MIPS_CPU_LLSC;
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c->tlbsize = 32;
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c->tlbsize = 32;
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@ -822,6 +866,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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c->cputype = CPU_R6000A;
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c->cputype = CPU_R6000A;
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__cpu_name[cpu] = "R6000A";
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__cpu_name[cpu] = "R6000A";
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set_isa(c, MIPS_CPU_ISA_II);
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set_isa(c, MIPS_CPU_ISA_II);
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c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
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c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
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c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
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MIPS_CPU_LLSC;
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MIPS_CPU_LLSC;
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c->tlbsize = 32;
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c->tlbsize = 32;
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@ -893,12 +938,14 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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__cpu_name[cpu] = "ICT Loongson-2";
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__cpu_name[cpu] = "ICT Loongson-2";
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set_elf_platform(cpu, "loongson2e");
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set_elf_platform(cpu, "loongson2e");
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set_isa(c, MIPS_CPU_ISA_III);
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set_isa(c, MIPS_CPU_ISA_III);
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c->fpu_msk31 |= FPU_CSR_CONDX;
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break;
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break;
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case PRID_REV_LOONGSON2F:
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case PRID_REV_LOONGSON2F:
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c->cputype = CPU_LOONGSON2;
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c->cputype = CPU_LOONGSON2;
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__cpu_name[cpu] = "ICT Loongson-2";
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__cpu_name[cpu] = "ICT Loongson-2";
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set_elf_platform(cpu, "loongson2f");
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set_elf_platform(cpu, "loongson2f");
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set_isa(c, MIPS_CPU_ISA_III);
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set_isa(c, MIPS_CPU_ISA_III);
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c->fpu_msk31 |= FPU_CSR_CONDX;
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break;
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break;
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case PRID_REV_LOONGSON3A:
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case PRID_REV_LOONGSON3A:
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c->cputype = CPU_LOONGSON3;
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c->cputype = CPU_LOONGSON3;
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@ -1335,6 +1382,9 @@ void cpu_probe(void)
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c->cputype = CPU_UNKNOWN;
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c->cputype = CPU_UNKNOWN;
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c->writecombine = _CACHE_UNCACHED;
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c->writecombine = _CACHE_UNCACHED;
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c->fpu_csr31 = FPU_CSR_RN;
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c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
|
||||||
|
|
||||||
c->processor_id = read_c0_prid();
|
c->processor_id = read_c0_prid();
|
||||||
switch (c->processor_id & PRID_COMP_MASK) {
|
switch (c->processor_id & PRID_COMP_MASK) {
|
||||||
case PRID_COMP_LEGACY:
|
case PRID_COMP_LEGACY:
|
||||||
@ -1393,6 +1443,7 @@ void cpu_probe(void)
|
|||||||
|
|
||||||
if (c->options & MIPS_CPU_FPU) {
|
if (c->options & MIPS_CPU_FPU) {
|
||||||
c->fpu_id = cpu_get_fpu_id();
|
c->fpu_id = cpu_get_fpu_id();
|
||||||
|
mips_nofpu_msk31 = c->fpu_msk31;
|
||||||
|
|
||||||
if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
|
if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
|
||||||
MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
|
MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
|
||||||
@ -1402,6 +1453,8 @@ void cpu_probe(void)
|
|||||||
if (c->fpu_id & MIPS_FPIR_FREP)
|
if (c->fpu_id & MIPS_FPIR_FREP)
|
||||||
c->options |= MIPS_CPU_FRE;
|
c->options |= MIPS_CPU_FRE;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
cpu_set_fpu_fcsr_mask(c);
|
||||||
} else
|
} else
|
||||||
cpu_set_nofpu_id(c);
|
cpu_set_nofpu_id(c);
|
||||||
|
|
||||||
|
@ -32,6 +32,7 @@
|
|||||||
|
|
||||||
#include <asm/byteorder.h>
|
#include <asm/byteorder.h>
|
||||||
#include <asm/cpu.h>
|
#include <asm/cpu.h>
|
||||||
|
#include <asm/cpu-info.h>
|
||||||
#include <asm/dsp.h>
|
#include <asm/dsp.h>
|
||||||
#include <asm/fpu.h>
|
#include <asm/fpu.h>
|
||||||
#include <asm/mipsregs.h>
|
#include <asm/mipsregs.h>
|
||||||
@ -137,6 +138,9 @@ int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
|
|||||||
{
|
{
|
||||||
union fpureg *fregs;
|
union fpureg *fregs;
|
||||||
u64 fpr_val;
|
u64 fpr_val;
|
||||||
|
u32 fcr31;
|
||||||
|
u32 value;
|
||||||
|
u32 mask;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
if (!access_ok(VERIFY_READ, data, 33 * 8))
|
if (!access_ok(VERIFY_READ, data, 33 * 8))
|
||||||
@ -149,8 +153,10 @@ int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
|
|||||||
set_fpr64(&fregs[i], 0, fpr_val);
|
set_fpr64(&fregs[i], 0, fpr_val);
|
||||||
}
|
}
|
||||||
|
|
||||||
__get_user(child->thread.fpu.fcr31, data + 64);
|
__get_user(value, data + 64);
|
||||||
child->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
|
fcr31 = child->thread.fpu.fcr31;
|
||||||
|
mask = current_cpu_data.fpu_msk31;
|
||||||
|
child->thread.fpu.fcr31 = (value & ~mask) | (fcr31 & mask);
|
||||||
|
|
||||||
/* FIR may not be written. */
|
/* FIR may not be written. */
|
||||||
|
|
||||||
|
@ -115,11 +115,9 @@ LEAF(_restore_fp)
|
|||||||
* the property that no matter whether considered as single or as double
|
* the property that no matter whether considered as single or as double
|
||||||
* precision represents signaling NANS.
|
* precision represents signaling NANS.
|
||||||
*
|
*
|
||||||
* We initialize fcr31 to rounding to nearest, no exceptions.
|
* The value to initialize fcr31 to comes in $a0.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define FPU_DEFAULT 0x00000000
|
|
||||||
|
|
||||||
.set push
|
.set push
|
||||||
SET_HARDFLOAT
|
SET_HARDFLOAT
|
||||||
|
|
||||||
@ -129,8 +127,7 @@ LEAF(_init_fpu)
|
|||||||
or t0, t1
|
or t0, t1
|
||||||
mtc0 t0, CP0_STATUS
|
mtc0 t0, CP0_STATUS
|
||||||
|
|
||||||
li t1, FPU_DEFAULT
|
ctc1 a0, fcr31
|
||||||
ctc1 t1, fcr31
|
|
||||||
|
|
||||||
li t0, -1
|
li t0, -1
|
||||||
|
|
||||||
|
@ -165,11 +165,9 @@ LEAF(_init_msa_upper)
|
|||||||
* the property that no matter whether considered as single or as double
|
* the property that no matter whether considered as single or as double
|
||||||
* precision represents signaling NANS.
|
* precision represents signaling NANS.
|
||||||
*
|
*
|
||||||
* We initialize fcr31 to rounding to nearest, no exceptions.
|
* The value to initialize fcr31 to comes in $a0.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define FPU_DEFAULT 0x00000000
|
|
||||||
|
|
||||||
.set push
|
.set push
|
||||||
SET_HARDFLOAT
|
SET_HARDFLOAT
|
||||||
|
|
||||||
@ -180,8 +178,7 @@ LEAF(_init_fpu)
|
|||||||
mtc0 t0, CP0_STATUS
|
mtc0 t0, CP0_STATUS
|
||||||
enable_fpu_hazard
|
enable_fpu_hazard
|
||||||
|
|
||||||
li t1, FPU_DEFAULT
|
ctc1 a0, fcr31
|
||||||
ctc1 t1, fcr31
|
|
||||||
|
|
||||||
li t1, -1 # SNaN
|
li t1, -1 # SNaN
|
||||||
|
|
||||||
|
@ -43,7 +43,7 @@ static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action,
|
|||||||
if (!fpu_owned) {
|
if (!fpu_owned) {
|
||||||
set_thread_flag(TIF_USEDFPU);
|
set_thread_flag(TIF_USEDFPU);
|
||||||
if (!used_math()) {
|
if (!used_math()) {
|
||||||
_init_fpu();
|
_init_fpu(current->thread.fpu.fcr31);
|
||||||
set_used_math();
|
set_used_math();
|
||||||
} else
|
} else
|
||||||
_restore_fp(current);
|
_restore_fp(current);
|
||||||
|
@ -908,6 +908,7 @@ static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
|||||||
{
|
{
|
||||||
u32 fcr31 = ctx->fcr31;
|
u32 fcr31 = ctx->fcr31;
|
||||||
u32 value;
|
u32 value;
|
||||||
|
u32 mask;
|
||||||
|
|
||||||
if (MIPSInst_RT(ir) == 0)
|
if (MIPSInst_RT(ir) == 0)
|
||||||
value = 0;
|
value = 0;
|
||||||
@ -919,9 +920,9 @@ static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
|||||||
pr_debug("%p gpr[%d]->csr=%08x\n",
|
pr_debug("%p gpr[%d]->csr=%08x\n",
|
||||||
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
|
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
|
||||||
|
|
||||||
/* Don't write unsupported bits. */
|
/* Preserve read-only bits. */
|
||||||
fcr31 = value &
|
mask = current_cpu_data.fpu_msk31;
|
||||||
~(FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
|
fcr31 = (value & ~mask) | (fcr31 & mask);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case FPCREG_FENR:
|
case FPCREG_FENR:
|
||||||
|
Loading…
Reference in New Issue
Block a user