usb: musb dma: add cppi41 dma driver
This driver is currently used by musb' cppi41 couter part. I may merge both dma engine user of musb at some point but not just yet. The driver seems to work in RX/TX mode in host mode, tested on mass storage. I increaed the size of the TX / RX transfers and waited for the core code to cancel a transfers and it seems to recover. v2..3: - use mall transfers on RX side and check data toggle. - use rndis mode on tx side so we haveon interrupt for 4096 transfers. - remove custom "transferred" hack and use dmaengine_tx_status() to compute the total amount of data that has been transferred. - cancel transfers and reclaim descriptors v1..v2: - RX path added - dma mode 0 & 1 is working - device tree nodes re-created. Cc: Vinod Koul <vinod.koul@intel.com> Cc: Dan Williams <djbw@fb.com> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Sebastian Andrzej Siewior
Felipe Balbi
parent
97238b35d5
commit
9b3452d1fa
@ -193,6 +193,10 @@
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usb@47401800 {
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status = "okay";
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};
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dma@07402000 {
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status = "okay";
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};
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};
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i2c1: i2c@4802a000 {
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@ -383,6 +383,29 @@
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port-mode = <3>;
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power = <250>;
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phys = <&usb0_phy>;
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dmas = <&cppi41dma 0 0 &cppi41dma 1 0
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&cppi41dma 2 0 &cppi41dma 3 0
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&cppi41dma 4 0 &cppi41dma 5 0
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&cppi41dma 6 0 &cppi41dma 7 0
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&cppi41dma 8 0 &cppi41dma 9 0
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&cppi41dma 10 0 &cppi41dma 11 0
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&cppi41dma 12 0 &cppi41dma 13 0
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&cppi41dma 14 0 &cppi41dma 0 1
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&cppi41dma 1 1 &cppi41dma 2 1
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&cppi41dma 3 1 &cppi41dma 4 1
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&cppi41dma 5 1 &cppi41dma 6 1
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&cppi41dma 7 1 &cppi41dma 8 1
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&cppi41dma 9 1 &cppi41dma 10 1
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&cppi41dma 11 1 &cppi41dma 12 1
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&cppi41dma 13 1 &cppi41dma 14 1>;
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dma-names =
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"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
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"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
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"rx14", "rx15",
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"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
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"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
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"tx14", "tx15";
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};
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};
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@ -415,8 +438,46 @@
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port-mode = <3>;
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power = <250>;
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phys = <&usb1_phy>;
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dmas = <&cppi41dma 15 0 &cppi41dma 16 0
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&cppi41dma 17 0 &cppi41dma 18 0
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&cppi41dma 19 0 &cppi41dma 20 0
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&cppi41dma 21 0 &cppi41dma 22 0
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&cppi41dma 23 0 &cppi41dma 24 0
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&cppi41dma 25 0 &cppi41dma 26 0
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&cppi41dma 27 0 &cppi41dma 28 0
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&cppi41dma 29 0 &cppi41dma 15 1
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&cppi41dma 16 1 &cppi41dma 17 1
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&cppi41dma 18 1 &cppi41dma 19 1
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&cppi41dma 20 1 &cppi41dma 21 1
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&cppi41dma 22 1 &cppi41dma 23 1
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&cppi41dma 24 1 &cppi41dma 25 1
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&cppi41dma 26 1 &cppi41dma 27 1
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&cppi41dma 28 1 &cppi41dma 29 1>;
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dma-names =
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"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
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"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
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"rx14", "rx15",
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"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
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"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
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"tx14", "tx15";
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};
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};
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cppi41dma: dma@07402000 {
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compatible = "ti,am3359-cppi41";
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reg = <0x47400000 0x1000
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0x47402000 0x1000
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0x47403000 0x1000
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0x47404000 0x4000>;
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reg-names = "glue controller scheduler queuemgr";
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interrupts = <17>;
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interrupt-names = "glue";
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#dma-cells = <2>;
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#dma-channels = <30>;
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#dma-requests = <256>;
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status = "disabled";
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};
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};
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epwmss0: epwmss@48300000 {
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@ -287,6 +287,14 @@ config DMA_OMAP
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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config TI_CPPI41
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tristate "AM33xx CPPI41 DMA support"
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depends on ARCH_OMAP
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select DMA_ENGINE
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help
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The Communications Port Programming Interface (CPPI) 4.1 DMA engine
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is currently used by the USB driver on AM335x platforms.
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config MMP_PDMA
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bool "MMP PDMA support"
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depends on (ARCH_MMP || ARCH_PXA)
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@ -39,3 +39,4 @@ obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
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obj-$(CONFIG_DMA_OMAP) += omap-dma.o
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obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
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obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
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obj-$(CONFIG_TI_CPPI41) += cppi41.o
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1048
drivers/dma/cppi41.c
Normal file
1048
drivers/dma/cppi41.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -129,6 +129,10 @@ config USB_TI_CPPI_DMA
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help
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Enable DMA transfers when TI CPPI DMA is available.
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config USB_TI_CPPI41_DMA
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bool 'TI CPPI 4.1 (AM335x)'
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depends on ARCH_OMAP
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config USB_TUSB_OMAP_DMA
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bool 'TUSB 6010'
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depends on USB_MUSB_TUSB6010
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@ -32,3 +32,4 @@ musb_hdrc-$(CONFIG_USB_INVENTRA_DMA) += musbhsdma.o
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musb_hdrc-$(CONFIG_USB_TI_CPPI_DMA) += cppi_dma.o
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musb_hdrc-$(CONFIG_USB_TUSB_OMAP_DMA) += tusb6010_omap.o
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musb_hdrc-$(CONFIG_USB_UX500_DMA) += ux500_dma.o
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musb_hdrc-$(CONFIG_USB_TI_CPPI41_DMA) += musb_cppi41.o
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552
drivers/usb/musb/musb_cppi41.c
Normal file
552
drivers/usb/musb/musb_cppi41.c
Normal file
@ -0,0 +1,552 @@
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/sizes.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include "musb_core.h"
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#define RNDIS_REG(x) (0x80 + ((x - 1) * 4))
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#define EP_MODE_AUTOREG_NONE 0
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#define EP_MODE_AUTOREG_ALL_NEOP 1
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#define EP_MODE_AUTOREG_ALWAYS 3
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#define EP_MODE_DMA_TRANSPARENT 0
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#define EP_MODE_DMA_RNDIS 1
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#define EP_MODE_DMA_GEN_RNDIS 3
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#define USB_CTRL_TX_MODE 0x70
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#define USB_CTRL_RX_MODE 0x74
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#define USB_CTRL_AUTOREQ 0xd0
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#define USB_TDOWN 0xd8
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struct cppi41_dma_channel {
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struct dma_channel channel;
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struct cppi41_dma_controller *controller;
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struct musb_hw_ep *hw_ep;
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struct dma_chan *dc;
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dma_cookie_t cookie;
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u8 port_num;
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u8 is_tx;
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u8 is_allocated;
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u8 usb_toggle;
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dma_addr_t buf_addr;
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u32 total_len;
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u32 prog_len;
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u32 transferred;
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u32 packet_sz;
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};
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#define MUSB_DMA_NUM_CHANNELS 15
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struct cppi41_dma_controller {
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struct dma_controller controller;
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struct cppi41_dma_channel rx_channel[MUSB_DMA_NUM_CHANNELS];
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struct cppi41_dma_channel tx_channel[MUSB_DMA_NUM_CHANNELS];
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struct musb *musb;
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u32 rx_mode;
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u32 tx_mode;
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u32 auto_req;
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};
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static void save_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
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{
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u16 csr;
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u8 toggle;
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if (cppi41_channel->is_tx)
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return;
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if (!is_host_active(cppi41_channel->controller->musb))
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return;
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csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
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toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
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cppi41_channel->usb_toggle = toggle;
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}
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static void update_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
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{
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u16 csr;
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u8 toggle;
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if (cppi41_channel->is_tx)
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return;
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if (!is_host_active(cppi41_channel->controller->musb))
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return;
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csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
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toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
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/*
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* AM335x Advisory 1.0.13: Due to internal synchronisation error the
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* data toggle may reset from DATA1 to DATA0 during receiving data from
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* more than one endpoint.
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*/
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if (!toggle && toggle == cppi41_channel->usb_toggle) {
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csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE;
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musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr);
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dev_dbg(cppi41_channel->controller->musb->controller,
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"Restoring DATA1 toggle.\n");
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}
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cppi41_channel->usb_toggle = toggle;
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}
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static void cppi41_dma_callback(void *private_data)
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{
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struct dma_channel *channel = private_data;
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struct cppi41_dma_channel *cppi41_channel = channel->private_data;
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struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
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struct musb *musb = hw_ep->musb;
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unsigned long flags;
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struct dma_tx_state txstate;
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u32 transferred;
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spin_lock_irqsave(&musb->lock, flags);
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dmaengine_tx_status(cppi41_channel->dc, cppi41_channel->cookie,
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&txstate);
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transferred = cppi41_channel->prog_len - txstate.residue;
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cppi41_channel->transferred += transferred;
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dev_dbg(musb->controller, "DMA transfer done on hw_ep=%d bytes=%d/%d\n",
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hw_ep->epnum, cppi41_channel->transferred,
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cppi41_channel->total_len);
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update_rx_toggle(cppi41_channel);
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if (cppi41_channel->transferred == cppi41_channel->total_len ||
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transferred < cppi41_channel->packet_sz) {
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/* done, complete */
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cppi41_channel->channel.actual_len =
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cppi41_channel->transferred;
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cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
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musb_dma_completion(musb, hw_ep->epnum, cppi41_channel->is_tx);
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} else {
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/* next iteration, reload */
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struct dma_chan *dc = cppi41_channel->dc;
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struct dma_async_tx_descriptor *dma_desc;
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enum dma_transfer_direction direction;
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u16 csr;
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u32 remain_bytes;
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void __iomem *epio = cppi41_channel->hw_ep->regs;
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cppi41_channel->buf_addr += cppi41_channel->packet_sz;
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remain_bytes = cppi41_channel->total_len;
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remain_bytes -= cppi41_channel->transferred;
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remain_bytes = min(remain_bytes, cppi41_channel->packet_sz);
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cppi41_channel->prog_len = remain_bytes;
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direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV
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: DMA_DEV_TO_MEM;
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dma_desc = dmaengine_prep_slave_single(dc,
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cppi41_channel->buf_addr,
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remain_bytes,
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direction,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (WARN_ON(!dma_desc))
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return;
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dma_desc->callback = cppi41_dma_callback;
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dma_desc->callback_param = channel;
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cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
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dma_async_issue_pending(dc);
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if (!cppi41_channel->is_tx) {
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csr = musb_readw(epio, MUSB_RXCSR);
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csr |= MUSB_RXCSR_H_REQPKT;
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musb_writew(epio, MUSB_RXCSR, csr);
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}
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}
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spin_unlock_irqrestore(&musb->lock, flags);
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}
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static u32 update_ep_mode(unsigned ep, unsigned mode, u32 old)
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{
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unsigned shift;
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shift = (ep - 1) * 2;
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old &= ~(3 << shift);
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old |= mode << shift;
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return old;
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}
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static void cppi41_set_dma_mode(struct cppi41_dma_channel *cppi41_channel,
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unsigned mode)
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{
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struct cppi41_dma_controller *controller = cppi41_channel->controller;
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u32 port;
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u32 new_mode;
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u32 old_mode;
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if (cppi41_channel->is_tx)
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old_mode = controller->tx_mode;
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else
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old_mode = controller->rx_mode;
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port = cppi41_channel->port_num;
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new_mode = update_ep_mode(port, mode, old_mode);
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if (new_mode == old_mode)
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return;
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if (cppi41_channel->is_tx) {
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controller->tx_mode = new_mode;
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musb_writel(controller->musb->ctrl_base, USB_CTRL_TX_MODE,
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new_mode);
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} else {
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controller->rx_mode = new_mode;
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musb_writel(controller->musb->ctrl_base, USB_CTRL_RX_MODE,
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new_mode);
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}
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}
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static void cppi41_set_autoreq_mode(struct cppi41_dma_channel *cppi41_channel,
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unsigned mode)
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{
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struct cppi41_dma_controller *controller = cppi41_channel->controller;
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u32 port;
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u32 new_mode;
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u32 old_mode;
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old_mode = controller->auto_req;
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port = cppi41_channel->port_num;
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new_mode = update_ep_mode(port, mode, old_mode);
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if (new_mode == old_mode)
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return;
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controller->auto_req = new_mode;
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musb_writel(controller->musb->ctrl_base, USB_CTRL_AUTOREQ, new_mode);
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}
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static bool cppi41_configure_channel(struct dma_channel *channel,
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u16 packet_sz, u8 mode,
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dma_addr_t dma_addr, u32 len)
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{
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struct cppi41_dma_channel *cppi41_channel = channel->private_data;
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struct dma_chan *dc = cppi41_channel->dc;
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struct dma_async_tx_descriptor *dma_desc;
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enum dma_transfer_direction direction;
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struct musb *musb = cppi41_channel->controller->musb;
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unsigned use_gen_rndis = 0;
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dev_dbg(musb->controller,
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"configure ep%d/%x packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
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cppi41_channel->port_num, RNDIS_REG(cppi41_channel->port_num),
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packet_sz, mode, (unsigned long long) dma_addr,
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len, cppi41_channel->is_tx);
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cppi41_channel->buf_addr = dma_addr;
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cppi41_channel->total_len = len;
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cppi41_channel->transferred = 0;
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cppi41_channel->packet_sz = packet_sz;
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/*
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* Due to AM335x' Advisory 1.0.13 we are not allowed to transfer more
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* than max packet size at a time.
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*/
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if (cppi41_channel->is_tx)
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use_gen_rndis = 1;
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if (use_gen_rndis) {
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/* RNDIS mode */
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if (len > packet_sz) {
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musb_writel(musb->ctrl_base,
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RNDIS_REG(cppi41_channel->port_num), len);
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/* gen rndis */
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cppi41_set_dma_mode(cppi41_channel,
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EP_MODE_DMA_GEN_RNDIS);
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/* auto req */
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cppi41_set_autoreq_mode(cppi41_channel,
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EP_MODE_AUTOREG_ALL_NEOP);
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} else {
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musb_writel(musb->ctrl_base,
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RNDIS_REG(cppi41_channel->port_num), 0);
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cppi41_set_dma_mode(cppi41_channel,
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EP_MODE_DMA_TRANSPARENT);
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cppi41_set_autoreq_mode(cppi41_channel,
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EP_MODE_AUTOREG_NONE);
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}
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} else {
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/* fallback mode */
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cppi41_set_dma_mode(cppi41_channel, EP_MODE_DMA_TRANSPARENT);
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cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREG_NONE);
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len = min_t(u32, packet_sz, len);
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}
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cppi41_channel->prog_len = len;
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direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
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dma_desc = dmaengine_prep_slave_single(dc, dma_addr, len, direction,
|
||||
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
||||
if (!dma_desc)
|
||||
return false;
|
||||
|
||||
dma_desc->callback = cppi41_dma_callback;
|
||||
dma_desc->callback_param = channel;
|
||||
cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
|
||||
|
||||
save_rx_toggle(cppi41_channel);
|
||||
dma_async_issue_pending(dc);
|
||||
return true;
|
||||
}
|
||||
|
||||
static struct dma_channel *cppi41_dma_channel_allocate(struct dma_controller *c,
|
||||
struct musb_hw_ep *hw_ep, u8 is_tx)
|
||||
{
|
||||
struct cppi41_dma_controller *controller = container_of(c,
|
||||
struct cppi41_dma_controller, controller);
|
||||
struct cppi41_dma_channel *cppi41_channel = NULL;
|
||||
u8 ch_num = hw_ep->epnum - 1;
|
||||
|
||||
if (ch_num >= MUSB_DMA_NUM_CHANNELS)
|
||||
return NULL;
|
||||
|
||||
if (is_tx)
|
||||
cppi41_channel = &controller->tx_channel[ch_num];
|
||||
else
|
||||
cppi41_channel = &controller->rx_channel[ch_num];
|
||||
|
||||
if (!cppi41_channel->dc)
|
||||
return NULL;
|
||||
|
||||
if (cppi41_channel->is_allocated)
|
||||
return NULL;
|
||||
|
||||
cppi41_channel->hw_ep = hw_ep;
|
||||
cppi41_channel->is_allocated = 1;
|
||||
|
||||
return &cppi41_channel->channel;
|
||||
}
|
||||
|
||||
static void cppi41_dma_channel_release(struct dma_channel *channel)
|
||||
{
|
||||
struct cppi41_dma_channel *cppi41_channel = channel->private_data;
|
||||
|
||||
if (cppi41_channel->is_allocated) {
|
||||
cppi41_channel->is_allocated = 0;
|
||||
channel->status = MUSB_DMA_STATUS_FREE;
|
||||
channel->actual_len = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static int cppi41_dma_channel_program(struct dma_channel *channel,
|
||||
u16 packet_sz, u8 mode,
|
||||
dma_addr_t dma_addr, u32 len)
|
||||
{
|
||||
int ret;
|
||||
|
||||
BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
|
||||
channel->status == MUSB_DMA_STATUS_BUSY);
|
||||
|
||||
channel->status = MUSB_DMA_STATUS_BUSY;
|
||||
channel->actual_len = 0;
|
||||
ret = cppi41_configure_channel(channel, packet_sz, mode, dma_addr, len);
|
||||
if (!ret)
|
||||
channel->status = MUSB_DMA_STATUS_FREE;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int cppi41_is_compatible(struct dma_channel *channel, u16 maxpacket,
|
||||
void *buf, u32 length)
|
||||
{
|
||||
struct cppi41_dma_channel *cppi41_channel = channel->private_data;
|
||||
struct cppi41_dma_controller *controller = cppi41_channel->controller;
|
||||
struct musb *musb = controller->musb;
|
||||
|
||||
if (is_host_active(musb)) {
|
||||
WARN_ON(1);
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cppi41_dma_channel_abort(struct dma_channel *channel)
|
||||
{
|
||||
struct cppi41_dma_channel *cppi41_channel = channel->private_data;
|
||||
struct cppi41_dma_controller *controller = cppi41_channel->controller;
|
||||
struct musb *musb = controller->musb;
|
||||
void __iomem *epio = cppi41_channel->hw_ep->regs;
|
||||
int tdbit;
|
||||
int ret;
|
||||
unsigned is_tx;
|
||||
u16 csr;
|
||||
|
||||
is_tx = cppi41_channel->is_tx;
|
||||
dev_dbg(musb->controller, "abort channel=%d, is_tx=%d\n",
|
||||
cppi41_channel->port_num, is_tx);
|
||||
|
||||
if (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)
|
||||
return 0;
|
||||
|
||||
if (is_tx) {
|
||||
csr = musb_readw(epio, MUSB_TXCSR);
|
||||
csr &= ~MUSB_TXCSR_DMAENAB;
|
||||
musb_writew(epio, MUSB_TXCSR, csr);
|
||||
} else {
|
||||
csr = musb_readw(epio, MUSB_RXCSR);
|
||||
csr &= ~(MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_DMAENAB);
|
||||
musb_writew(epio, MUSB_RXCSR, csr);
|
||||
|
||||
csr = musb_readw(epio, MUSB_RXCSR);
|
||||
if (csr & MUSB_RXCSR_RXPKTRDY) {
|
||||
csr |= MUSB_RXCSR_FLUSHFIFO;
|
||||
musb_writew(epio, MUSB_RXCSR, csr);
|
||||
musb_writew(epio, MUSB_RXCSR, csr);
|
||||
}
|
||||
}
|
||||
|
||||
tdbit = 1 << cppi41_channel->port_num;
|
||||
if (is_tx)
|
||||
tdbit <<= 16;
|
||||
|
||||
do {
|
||||
musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
|
||||
ret = dmaengine_terminate_all(cppi41_channel->dc);
|
||||
} while (ret == -EAGAIN);
|
||||
|
||||
musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
|
||||
|
||||
if (is_tx) {
|
||||
csr = musb_readw(epio, MUSB_TXCSR);
|
||||
if (csr & MUSB_TXCSR_TXPKTRDY) {
|
||||
csr |= MUSB_TXCSR_FLUSHFIFO;
|
||||
musb_writew(epio, MUSB_TXCSR, csr);
|
||||
}
|
||||
}
|
||||
|
||||
cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void cppi41_release_all_dma_chans(struct cppi41_dma_controller *ctrl)
|
||||
{
|
||||
struct dma_chan *dc;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < MUSB_DMA_NUM_CHANNELS; i++) {
|
||||
dc = ctrl->tx_channel[i].dc;
|
||||
if (dc)
|
||||
dma_release_channel(dc);
|
||||
dc = ctrl->rx_channel[i].dc;
|
||||
if (dc)
|
||||
dma_release_channel(dc);
|
||||
}
|
||||
}
|
||||
|
||||
static void cppi41_dma_controller_stop(struct cppi41_dma_controller *controller)
|
||||
{
|
||||
cppi41_release_all_dma_chans(controller);
|
||||
}
|
||||
|
||||
static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller)
|
||||
{
|
||||
struct musb *musb = controller->musb;
|
||||
struct device *dev = musb->controller;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct cppi41_dma_channel *cppi41_channel;
|
||||
int count;
|
||||
int i;
|
||||
int ret;
|
||||
|
||||
count = of_property_count_strings(np, "dma-names");
|
||||
if (count < 0)
|
||||
return count;
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
struct dma_chan *dc;
|
||||
struct dma_channel *musb_dma;
|
||||
const char *str;
|
||||
unsigned is_tx;
|
||||
unsigned int port;
|
||||
|
||||
ret = of_property_read_string_index(np, "dma-names", i, &str);
|
||||
if (ret)
|
||||
goto err;
|
||||
if (!strncmp(str, "tx", 2))
|
||||
is_tx = 1;
|
||||
else if (!strncmp(str, "rx", 2))
|
||||
is_tx = 0;
|
||||
else {
|
||||
dev_err(dev, "Wrong dmatype %s\n", str);
|
||||
goto err;
|
||||
}
|
||||
ret = kstrtouint(str + 2, 0, &port);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
if (port > MUSB_DMA_NUM_CHANNELS || !port)
|
||||
goto err;
|
||||
if (is_tx)
|
||||
cppi41_channel = &controller->tx_channel[port - 1];
|
||||
else
|
||||
cppi41_channel = &controller->rx_channel[port - 1];
|
||||
|
||||
cppi41_channel->controller = controller;
|
||||
cppi41_channel->port_num = port;
|
||||
cppi41_channel->is_tx = is_tx;
|
||||
|
||||
musb_dma = &cppi41_channel->channel;
|
||||
musb_dma->private_data = cppi41_channel;
|
||||
musb_dma->status = MUSB_DMA_STATUS_FREE;
|
||||
musb_dma->max_len = SZ_4M;
|
||||
|
||||
dc = dma_request_slave_channel(dev, str);
|
||||
if (!dc) {
|
||||
dev_err(dev, "Falied to request %s.\n", str);
|
||||
goto err;
|
||||
}
|
||||
cppi41_channel->dc = dc;
|
||||
}
|
||||
return 0;
|
||||
err:
|
||||
cppi41_release_all_dma_chans(controller);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
void dma_controller_destroy(struct dma_controller *c)
|
||||
{
|
||||
struct cppi41_dma_controller *controller = container_of(c,
|
||||
struct cppi41_dma_controller, controller);
|
||||
|
||||
cppi41_dma_controller_stop(controller);
|
||||
kfree(controller);
|
||||
}
|
||||
|
||||
struct dma_controller *dma_controller_create(struct musb *musb,
|
||||
void __iomem *base)
|
||||
{
|
||||
struct cppi41_dma_controller *controller;
|
||||
int ret;
|
||||
|
||||
if (!musb->controller->of_node) {
|
||||
dev_err(musb->controller, "Need DT for the DMA engine.\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
controller = kzalloc(sizeof(*controller), GFP_KERNEL);
|
||||
if (!controller)
|
||||
goto kzalloc_fail;
|
||||
|
||||
controller->musb = musb;
|
||||
|
||||
controller->controller.channel_alloc = cppi41_dma_channel_allocate;
|
||||
controller->controller.channel_release = cppi41_dma_channel_release;
|
||||
controller->controller.channel_program = cppi41_dma_channel_program;
|
||||
controller->controller.channel_abort = cppi41_dma_channel_abort;
|
||||
controller->controller.is_compatible = cppi41_is_compatible;
|
||||
|
||||
ret = cppi41_dma_controller_start(controller);
|
||||
if (ret)
|
||||
goto plat_get_fail;
|
||||
return &controller->controller;
|
||||
|
||||
plat_get_fail:
|
||||
kfree(controller);
|
||||
kzalloc_fail:
|
||||
return NULL;
|
||||
}
|
||||
@ -68,7 +68,7 @@ struct musb_hw_ep;
|
||||
#define is_dma_capable() (1)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_TI_CPPI_DMA
|
||||
#if defined(CONFIG_USB_TI_CPPI_DMA) || defined(CONFIG_USB_TI_CPPI41_DMA)
|
||||
#define is_cppi_enabled() 1
|
||||
#else
|
||||
#define is_cppi_enabled() 0
|
||||
|
||||
Loading…
Reference in New Issue
Block a user