From bd79d9aa6145897c0180964e8e68fcf9ba6b2206 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Wed, 7 Apr 2021 22:22:39 +0200
Subject: [PATCH 01/16] net: phy: marvell10g: rename register
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The MV_V2_PORT_MAC_TYPE_* is part of the CTRL register. Rename to
MV_V2_PORT_CTRL_MACTYPE_*.
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/phy/marvell10g.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 74b64e52ffa2..9b514124af0d 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -80,8 +80,8 @@ enum {
MV_V2_PORT_CTRL = 0xf001,
MV_V2_PORT_CTRL_SWRST = BIT(15),
MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
- MV_V2_PORT_MAC_TYPE_MASK = 0x7,
- MV_V2_PORT_MAC_TYPE_RATE_MATCH = 0x6,
+ MV_V2_PORT_CTRL_MACTYPE_MASK = 0x7,
+ MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6,
/* Temperature control/read registers (88X3310 only) */
MV_V2_TEMP_CTRL = 0xf08a,
MV_V2_TEMP_CTRL_MASK = 0xc000,
@@ -477,8 +477,8 @@ static int mv3310_config_init(struct phy_device *phydev)
val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
if (val < 0)
return val;
- priv->rate_match = ((val & MV_V2_PORT_MAC_TYPE_MASK) ==
- MV_V2_PORT_MAC_TYPE_RATE_MATCH);
+ priv->rate_match = ((val & MV_V2_PORT_CTRL_MACTYPE_MASK) ==
+ MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH);
/* Enable EDPD mode - saving 600mW */
return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
From 283828142fad71a6bab4c1a6b0ba28c323fd36a0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Wed, 7 Apr 2021 22:22:40 +0200
Subject: [PATCH 02/16] net: phy: marvell10g: fix typo
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This space should be a tab instead.
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/phy/marvell10g.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 9b514124af0d..f2f0da9717be 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -79,7 +79,7 @@ enum {
/* Vendor2 MMD registers */
MV_V2_PORT_CTRL = 0xf001,
MV_V2_PORT_CTRL_SWRST = BIT(15),
- MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
+ MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
MV_V2_PORT_CTRL_MACTYPE_MASK = 0x7,
MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6,
/* Temperature control/read registers (88X3310 only) */
From 0d3755428d6990637cf6dc45f007980a1dce28d1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Wed, 7 Apr 2021 22:22:41 +0200
Subject: [PATCH 03/16] net: phy: marvell10g: allow 5gbase-r and usxgmii
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
These modes are also supported by these PHYs.
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/phy/marvell10g.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index f2f0da9717be..881a0717846e 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -462,9 +462,11 @@ static int mv3310_config_init(struct phy_device *phydev)
/* Check that the PHY interface type is compatible */
if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
+ phydev->interface != PHY_INTERFACE_MODE_5GBASER &&
phydev->interface != PHY_INTERFACE_MODE_XAUI &&
phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
- phydev->interface != PHY_INTERFACE_MODE_10GBASER)
+ phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
+ phydev->interface != PHY_INTERFACE_MODE_USXGMII)
return -ENODEV;
phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
@@ -599,6 +601,7 @@ static void mv3310_update_interface(struct phy_device *phydev)
if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
+ phydev->interface == PHY_INTERFACE_MODE_5GBASER ||
phydev->interface == PHY_INTERFACE_MODE_10GBASER) &&
phydev->link) {
/* The PHY automatically switches its serdes interface (and
@@ -611,6 +614,9 @@ static void mv3310_update_interface(struct phy_device *phydev)
case SPEED_10000:
phydev->interface = PHY_INTERFACE_MODE_10GBASER;
break;
+ case SPEED_5000:
+ phydev->interface = PHY_INTERFACE_MODE_5GBASER;
+ break;
case SPEED_2500:
phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
break;
From 9893f31690162bf90ef7f85d9dda80731696d586 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Wed, 7 Apr 2021 22:22:42 +0200
Subject: [PATCH 04/16] net: phy: marvell10g: indicate 88X33x0 only port
control registers
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Rename port control registers to indicate that they are valid only for
88X33x0, not for 88E21x0.
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/phy/marvell10g.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 881a0717846e..7552a658a513 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -78,10 +78,10 @@ enum {
/* Vendor2 MMD registers */
MV_V2_PORT_CTRL = 0xf001,
- MV_V2_PORT_CTRL_SWRST = BIT(15),
- MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
- MV_V2_PORT_CTRL_MACTYPE_MASK = 0x7,
- MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6,
+ MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
+ MV_V2_33X0_PORT_CTRL_SWRST = BIT(15),
+ MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7,
+ MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6,
/* Temperature control/read registers (88X3310 only) */
MV_V2_TEMP_CTRL = 0xf08a,
MV_V2_TEMP_CTRL_MASK = 0xc000,
@@ -268,7 +268,7 @@ static int mv3310_power_up(struct phy_device *phydev)
return ret;
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
- MV_V2_PORT_CTRL_SWRST);
+ MV_V2_33X0_PORT_CTRL_SWRST);
}
static int mv3310_reset(struct phy_device *phydev, u32 unit)
@@ -479,8 +479,8 @@ static int mv3310_config_init(struct phy_device *phydev)
val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
if (val < 0)
return val;
- priv->rate_match = ((val & MV_V2_PORT_CTRL_MACTYPE_MASK) ==
- MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH);
+ priv->rate_match = ((val & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK) ==
+ MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH);
/* Enable EDPD mode - saving 600mW */
return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
From f8ee45fcbc5a94177d031b22f4e5a47d45874037 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Wed, 7 Apr 2021 22:22:43 +0200
Subject: [PATCH 05/16] net: phy: marvell10g: add all MACTYPE definitions for
88X33x0
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add all MACTYPE definitions for 88X3310, 88X3310P, 88X3340 and 88X3340P.
In order to have consistent naming, rename
MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH to
MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH.
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/phy/marvell10g.c | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 7552a658a513..7d9a45437b69 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -78,10 +78,18 @@ enum {
/* Vendor2 MMD registers */
MV_V2_PORT_CTRL = 0xf001,
- MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
- MV_V2_33X0_PORT_CTRL_SWRST = BIT(15),
- MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7,
- MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6,
+ MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
+ MV_V2_33X0_PORT_CTRL_SWRST = BIT(15),
+ MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7,
+ MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI = 0x0,
+ MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH = 0x1,
+ MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN = 0x1,
+ MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH = 0x2,
+ MV_V2_3310_PORT_CTRL_MACTYPE_XAUI = 0x3,
+ MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER = 0x4,
+ MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN = 0x5,
+ MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
+ MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII = 0x7,
/* Temperature control/read registers (88X3310 only) */
MV_V2_TEMP_CTRL = 0xf08a,
MV_V2_TEMP_CTRL_MASK = 0xc000,
@@ -480,7 +488,7 @@ static int mv3310_config_init(struct phy_device *phydev)
if (val < 0)
return val;
priv->rate_match = ((val & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK) ==
- MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH);
+ MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH);
/* Enable EDPD mode - saving 600mW */
return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
From 9ab0fbd0ffcebe0ba95f7f05af49bea273ffd4db Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Wed, 7 Apr 2021 22:22:44 +0200
Subject: [PATCH 06/16] net: phy: marvell10g: add MACTYPE definitions for
88E21xx
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add all MACTYPE definitions for 88E2110, 88E2180, 88E2111 and 88E2181.
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/phy/marvell10g.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 7d9a45437b69..556c9b43860e 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -35,6 +35,15 @@
enum {
MV_PMA_FW_VER0 = 0xc011,
MV_PMA_FW_VER1 = 0xc012,
+ MV_PMA_21X0_PORT_CTRL = 0xc04a,
+ MV_PMA_21X0_PORT_CTRL_SWRST = BIT(15),
+ MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK = 0x7,
+ MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII = 0x0,
+ MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII = 0x1,
+ MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII = 0x2,
+ MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER = 0x4,
+ MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN = 0x5,
+ MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
MV_PMA_BOOT = 0xc050,
MV_PMA_BOOT_FATAL = BIT(0),
From 97bbe3bd6922e7ccf8ecd308640a7da55ae3c2f9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Wed, 7 Apr 2021 22:22:45 +0200
Subject: [PATCH 07/16] net: phy: marvell10g: support all rate matching modes
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add support for all rate matching modes for 88X3310 (currently only
10gbase-r is supported, but xaui and rxaui can also be used).
Add support for rate matching for 88E2110 (on 88E2110 the MACTYPE
register is at a different place).
Currently rate matching mode is selected by strapping pins (by setting
the MACTYPE register). There is work in progress to enable this driver
to deduce the best MACTYPE from the knowledge of which interface modes
are supported by the host, but this work is not finished yet.
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/phy/marvell10g.c | 103 +++++++++++++++++++++++++++++++----
1 file changed, 92 insertions(+), 11 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 556c9b43860e..b0b3fccac65f 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -108,14 +108,25 @@ enum {
MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */
};
+struct mv3310_chip {
+ int (*get_mactype)(struct phy_device *phydev);
+ int (*init_interface)(struct phy_device *phydev, int mactype);
+};
+
struct mv3310_priv {
u32 firmware_ver;
bool rate_match;
+ phy_interface_t const_interface;
struct device *hwmon_dev;
char *hwmon_name;
};
+static const struct mv3310_chip *to_mv3310_chip(struct phy_device *phydev)
+{
+ return phydev->drv->driver_data;
+}
+
#ifdef CONFIG_HWMON
static umode_t mv3310_hwmon_is_visible(const void *data,
enum hwmon_sensor_types type,
@@ -470,11 +481,67 @@ static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV;
}
-static int mv3310_config_init(struct phy_device *phydev)
+static int mv2110_get_mactype(struct phy_device *phydev)
+{
+ int mactype;
+
+ mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL);
+ if (mactype < 0)
+ return mactype;
+
+ return mactype & MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
+}
+
+static int mv3310_get_mactype(struct phy_device *phydev)
+{
+ int mactype;
+
+ mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
+ if (mactype < 0)
+ return mactype;
+
+ return mactype & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
+}
+
+static int mv2110_init_interface(struct phy_device *phydev, int mactype)
{
struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
- int err;
- int val;
+
+ priv->rate_match = false;
+
+ if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) {
+ priv->rate_match = true;
+ priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
+ }
+
+ return 0;
+}
+
+static int mv3310_init_interface(struct phy_device *phydev, int mactype)
+{
+ struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
+
+ priv->rate_match = false;
+
+ if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||
+ mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||
+ mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH)
+ priv->rate_match = true;
+
+ if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
+ priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
+ else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH)
+ priv->const_interface = PHY_INTERFACE_MODE_RXAUI;
+ else if (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH)
+ priv->const_interface = PHY_INTERFACE_MODE_XAUI;
+
+ return 0;
+}
+
+static int mv3310_config_init(struct phy_device *phydev)
+{
+ const struct mv3310_chip *chip = to_mv3310_chip(phydev);
+ int err, mactype;
/* Check that the PHY interface type is compatible */
if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
@@ -493,11 +560,13 @@ static int mv3310_config_init(struct phy_device *phydev)
if (err)
return err;
- val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
- if (val < 0)
- return val;
- priv->rate_match = ((val & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK) ==
- MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH);
+ mactype = chip->get_mactype(phydev);
+ if (mactype < 0)
+ return mactype;
+
+ err = chip->init_interface(phydev, mactype);
+ if (err)
+ return err;
/* Enable EDPD mode - saving 600mW */
return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
@@ -607,12 +676,12 @@ static void mv3310_update_interface(struct phy_device *phydev)
{
struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
- /* In "XFI with Rate Matching" mode the PHY interface is fixed at
- * 10Gb. The PHY adapts the rate to actual wire speed with help of
+ /* In all of the "* with Rate Matching" modes the PHY interface is fixed
+ * at 10Gb. The PHY adapts the rate to actual wire speed with help of
* internal 16KB buffer.
*/
if (priv->rate_match) {
- phydev->interface = PHY_INTERFACE_MODE_10GBASER;
+ phydev->interface = priv->const_interface;
return;
}
@@ -788,11 +857,22 @@ static int mv3310_set_tunable(struct phy_device *phydev,
}
}
+static const struct mv3310_chip mv3310_type = {
+ .get_mactype = mv3310_get_mactype,
+ .init_interface = mv3310_init_interface,
+};
+
+static const struct mv3310_chip mv2110_type = {
+ .get_mactype = mv2110_get_mactype,
+ .init_interface = mv2110_init_interface,
+};
+
static struct phy_driver mv3310_drivers[] = {
{
.phy_id = MARVELL_PHY_ID_88X3310,
.phy_id_mask = MARVELL_PHY_ID_MASK,
.name = "mv88x3310",
+ .driver_data = &mv3310_type,
.get_features = mv3310_get_features,
.config_init = mv3310_config_init,
.probe = mv3310_probe,
@@ -810,6 +890,7 @@ static struct phy_driver mv3310_drivers[] = {
.phy_id = MARVELL_PHY_ID_88E2110,
.phy_id_mask = MARVELL_PHY_ID_MASK,
.name = "mv88x2110",
+ .driver_data = &mv2110_type,
.probe = mv3310_probe,
.suspend = mv3310_suspend,
.resume = mv3310_resume,
From 261a74c64bb67fbd9795e4ece94c2579f3c866f2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Wed, 7 Apr 2021 22:22:46 +0200
Subject: [PATCH 08/16] net: phy: marvell10g: check for correct supported
interface mode
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The 88E2110 does not support xaui nor rxaui modes. Check for correct
interface mode for different chips.
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/phy/marvell10g.c | 37 +++++++++++++++++++++++++++++-------
1 file changed, 30 insertions(+), 7 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index b0b3fccac65f..a7c6b1944b05 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -109,11 +109,14 @@ enum {
};
struct mv3310_chip {
+ void (*init_supported_interfaces)(unsigned long *mask);
int (*get_mactype)(struct phy_device *phydev);
int (*init_interface)(struct phy_device *phydev, int mactype);
};
struct mv3310_priv {
+ DECLARE_BITMAP(supported_interfaces, PHY_INTERFACE_MODE_MAX);
+
u32 firmware_ver;
bool rate_match;
phy_interface_t const_interface;
@@ -391,6 +394,7 @@ static const struct sfp_upstream_ops mv3310_sfp_ops = {
static int mv3310_probe(struct phy_device *phydev)
{
+ const struct mv3310_chip *chip = to_mv3310_chip(phydev);
struct mv3310_priv *priv;
u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
int ret;
@@ -440,6 +444,8 @@ static int mv3310_probe(struct phy_device *phydev)
if (ret)
return ret;
+ chip->init_supported_interfaces(priv->supported_interfaces);
+
return phy_sfp_probe(phydev, &mv3310_sfp_ops);
}
@@ -540,17 +546,12 @@ static int mv3310_init_interface(struct phy_device *phydev, int mactype)
static int mv3310_config_init(struct phy_device *phydev)
{
+ struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
const struct mv3310_chip *chip = to_mv3310_chip(phydev);
int err, mactype;
/* Check that the PHY interface type is compatible */
- if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
- phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
- phydev->interface != PHY_INTERFACE_MODE_5GBASER &&
- phydev->interface != PHY_INTERFACE_MODE_XAUI &&
- phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
- phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
- phydev->interface != PHY_INTERFACE_MODE_USXGMII)
+ if (!test_bit(phydev->interface, priv->supported_interfaces))
return -ENODEV;
phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
@@ -857,12 +858,34 @@ static int mv3310_set_tunable(struct phy_device *phydev,
}
}
+static void mv3310_init_supported_interfaces(unsigned long *mask)
+{
+ __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
+ __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
+ __set_bit(PHY_INTERFACE_MODE_XAUI, mask);
+ __set_bit(PHY_INTERFACE_MODE_RXAUI, mask);
+ __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
+}
+
+static void mv2110_init_supported_interfaces(unsigned long *mask)
+{
+ __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
+ __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
+ __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
+}
+
static const struct mv3310_chip mv3310_type = {
+ .init_supported_interfaces = mv3310_init_supported_interfaces,
.get_mactype = mv3310_get_mactype,
.init_interface = mv3310_init_interface,
};
static const struct mv3310_chip mv2110_type = {
+ .init_supported_interfaces = mv2110_init_supported_interfaces,
.get_mactype = mv2110_get_mactype,
.init_interface = mv2110_init_interface,
};
From 884d9a6758a1a704367e7bb3d3cc814a6fe8f20c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Wed, 7 Apr 2021 22:22:47 +0200
Subject: [PATCH 09/16] net: phy: marvell10g: store temperature read method in
chip strucutre
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Now that we have a chip structure, we can store the temperature reading
method in this structure (OOP style).
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/phy/marvell10g.c | 23 ++++++++++++++---------
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index a7c6b1944b05..20d3e572c935 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -112,6 +112,10 @@ struct mv3310_chip {
void (*init_supported_interfaces)(unsigned long *mask);
int (*get_mactype)(struct phy_device *phydev);
int (*init_interface)(struct phy_device *phydev, int mactype);
+
+#ifdef CONFIG_HWMON
+ int (*hwmon_read_temp_reg)(struct phy_device *phydev);
+#endif
};
struct mv3310_priv {
@@ -152,18 +156,11 @@ static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev)
return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP);
}
-static int mv10g_hwmon_read_temp_reg(struct phy_device *phydev)
-{
- if (phydev->drv->phy_id == MARVELL_PHY_ID_88X3310)
- return mv3310_hwmon_read_temp_reg(phydev);
- else /* MARVELL_PHY_ID_88E2110 */
- return mv2110_hwmon_read_temp_reg(phydev);
-}
-
static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *value)
{
struct phy_device *phydev = dev_get_drvdata(dev);
+ const struct mv3310_chip *chip = to_mv3310_chip(phydev);
int temp;
if (type == hwmon_chip && attr == hwmon_chip_update_interval) {
@@ -172,7 +169,7 @@ static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
}
if (type == hwmon_temp && attr == hwmon_temp_input) {
- temp = mv10g_hwmon_read_temp_reg(phydev);
+ temp = chip->hwmon_read_temp_reg(phydev);
if (temp < 0)
return temp;
@@ -882,12 +879,20 @@ static const struct mv3310_chip mv3310_type = {
.init_supported_interfaces = mv3310_init_supported_interfaces,
.get_mactype = mv3310_get_mactype,
.init_interface = mv3310_init_interface,
+
+#ifdef CONFIG_HWMON
+ .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,
+#endif
};
static const struct mv3310_chip mv2110_type = {
.init_supported_interfaces = mv2110_init_supported_interfaces,
.get_mactype = mv2110_get_mactype,
.init_interface = mv2110_init_interface,
+
+#ifdef CONFIG_HWMON
+ .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,
+#endif
};
static struct phy_driver mv3310_drivers[] = {
From ccbf2891de9813fc35b6f35cee97731532e9d386 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Wed, 7 Apr 2021 22:22:48 +0200
Subject: [PATCH 10/16] net: phy: marvell10g: support other MACTYPEs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Currently the only "changing" MACTYPE we support is when the PHY changes
between
10gbase-r / 5gbase-r / 2500base-x / sgmii
Add support for
usxgmii
xaui / 5gbase-r / 2500base-x / sgmii
rxaui / 5gbase-r / 2500base-x / sgmii
and also
5gbase-r / 2500base-x / sgmii
for 88E2110.
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/phy/marvell10g.c | 90 +++++++++++++++++++++---------------
1 file changed, 54 insertions(+), 36 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 20d3e572c935..2dc1317e601e 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -512,10 +512,18 @@ static int mv2110_init_interface(struct phy_device *phydev, int mactype)
priv->rate_match = false;
- if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) {
+ if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
priv->rate_match = true;
+
+ if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII)
+ priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
+ else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
- }
+ else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER ||
+ mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN)
+ priv->const_interface = PHY_INTERFACE_MODE_NA;
+ else
+ return -EINVAL;
return 0;
}
@@ -531,12 +539,20 @@ static int mv3310_init_interface(struct phy_device *phydev, int mactype)
mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH)
priv->rate_match = true;
- if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
+ if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII)
+ priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
+ else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||
+ mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN ||
+ mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER)
priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
- else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH)
+ else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||
+ mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI)
priv->const_interface = PHY_INTERFACE_MODE_RXAUI;
- else if (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH)
+ else if (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH ||
+ mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI)
priv->const_interface = PHY_INTERFACE_MODE_XAUI;
+ else
+ return -EINVAL;
return 0;
}
@@ -563,8 +579,10 @@ static int mv3310_config_init(struct phy_device *phydev)
return mactype;
err = chip->init_interface(phydev, mactype);
- if (err)
+ if (err) {
+ phydev_err(phydev, "MACTYPE configuration invalid\n");
return err;
+ }
/* Enable EDPD mode - saving 600mW */
return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
@@ -674,44 +692,44 @@ static void mv3310_update_interface(struct phy_device *phydev)
{
struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
+ if (!phydev->link)
+ return;
+
/* In all of the "* with Rate Matching" modes the PHY interface is fixed
* at 10Gb. The PHY adapts the rate to actual wire speed with help of
* internal 16KB buffer.
+ *
+ * In USXGMII mode the PHY interface mode is also fixed.
*/
- if (priv->rate_match) {
+ if (priv->rate_match ||
+ priv->const_interface == PHY_INTERFACE_MODE_USXGMII) {
phydev->interface = priv->const_interface;
return;
}
- if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
- phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
- phydev->interface == PHY_INTERFACE_MODE_5GBASER ||
- phydev->interface == PHY_INTERFACE_MODE_10GBASER) &&
- phydev->link) {
- /* The PHY automatically switches its serdes interface (and
- * active PHYXS instance) between Cisco SGMII, 10GBase-R and
- * 2500BaseX modes according to the speed. Florian suggests
- * setting phydev->interface to communicate this to the MAC.
- * Only do this if we are already in one of the above modes.
- */
- switch (phydev->speed) {
- case SPEED_10000:
- phydev->interface = PHY_INTERFACE_MODE_10GBASER;
- break;
- case SPEED_5000:
- phydev->interface = PHY_INTERFACE_MODE_5GBASER;
- break;
- case SPEED_2500:
- phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
- break;
- case SPEED_1000:
- case SPEED_100:
- case SPEED_10:
- phydev->interface = PHY_INTERFACE_MODE_SGMII;
- break;
- default:
- break;
- }
+ /* The PHY automatically switches its serdes interface (and active PHYXS
+ * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R /
+ * xaui / rxaui modes according to the speed.
+ * Florian suggests setting phydev->interface to communicate this to the
+ * MAC. Only do this if we are already in one of the above modes.
+ */
+ switch (phydev->speed) {
+ case SPEED_10000:
+ phydev->interface = priv->const_interface;
+ break;
+ case SPEED_5000:
+ phydev->interface = PHY_INTERFACE_MODE_5GBASER;
+ break;
+ case SPEED_2500:
+ phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
+ break;
+ case SPEED_1000:
+ case SPEED_100:
+ case SPEED_10:
+ phydev->interface = PHY_INTERFACE_MODE_SGMII;
+ break;
+ default:
+ break;
}
}
From 9885d016ffa9465f91498e7a70c413c30446ad49 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Wed, 7 Apr 2021 22:22:49 +0200
Subject: [PATCH 11/16] net: phy: marvell10g: add separate structure for
88X3340
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The 88X3340 contains 4 cores similar to 88X3310, but there is a
difference: it does not support xaui host mode. Instead the
corresponding MACTYPE means
rxaui / 5gbase-r / 2500base-x / sgmii without AN
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/phy/marvell10g.c | 58 ++++++++++++++++++++++++++++++++++--
include/linux/marvell_phy.h | 6 +++-
2 files changed, 61 insertions(+), 3 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 2dc1317e601e..f74dfd993d8b 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -557,6 +557,21 @@ static int mv3310_init_interface(struct phy_device *phydev, int mactype)
return 0;
}
+static int mv3340_init_interface(struct phy_device *phydev, int mactype)
+{
+ struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
+ int err = 0;
+
+ priv->rate_match = false;
+
+ if (mactype == MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN)
+ priv->const_interface = PHY_INTERFACE_MODE_RXAUI;
+ else
+ err = mv3310_init_interface(phydev, mactype);
+
+ return err;
+}
+
static int mv3310_config_init(struct phy_device *phydev)
{
struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
@@ -884,6 +899,16 @@ static void mv3310_init_supported_interfaces(unsigned long *mask)
__set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
}
+static void mv3340_init_supported_interfaces(unsigned long *mask)
+{
+ __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
+ __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
+ __set_bit(PHY_INTERFACE_MODE_RXAUI, mask);
+ __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
+}
+
static void mv2110_init_supported_interfaces(unsigned long *mask)
{
__set_bit(PHY_INTERFACE_MODE_SGMII, mask);
@@ -903,6 +928,16 @@ static const struct mv3310_chip mv3310_type = {
#endif
};
+static const struct mv3310_chip mv3340_type = {
+ .init_supported_interfaces = mv3340_init_supported_interfaces,
+ .get_mactype = mv3310_get_mactype,
+ .init_interface = mv3340_init_interface,
+
+#ifdef CONFIG_HWMON
+ .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,
+#endif
+};
+
static const struct mv3310_chip mv2110_type = {
.init_supported_interfaces = mv2110_init_supported_interfaces,
.get_mactype = mv2110_get_mactype,
@@ -916,7 +951,7 @@ static const struct mv3310_chip mv2110_type = {
static struct phy_driver mv3310_drivers[] = {
{
.phy_id = MARVELL_PHY_ID_88X3310,
- .phy_id_mask = MARVELL_PHY_ID_MASK,
+ .phy_id_mask = MARVELL_PHY_ID_88X33X0_MASK,
.name = "mv88x3310",
.driver_data = &mv3310_type,
.get_features = mv3310_get_features,
@@ -932,6 +967,24 @@ static struct phy_driver mv3310_drivers[] = {
.remove = mv3310_remove,
.set_loopback = genphy_c45_loopback,
},
+ {
+ .phy_id = MARVELL_PHY_ID_88X3340,
+ .phy_id_mask = MARVELL_PHY_ID_88X33X0_MASK,
+ .name = "mv88x3340",
+ .driver_data = &mv3340_type,
+ .get_features = mv3310_get_features,
+ .config_init = mv3310_config_init,
+ .probe = mv3310_probe,
+ .suspend = mv3310_suspend,
+ .resume = mv3310_resume,
+ .config_aneg = mv3310_config_aneg,
+ .aneg_done = mv3310_aneg_done,
+ .read_status = mv3310_read_status,
+ .get_tunable = mv3310_get_tunable,
+ .set_tunable = mv3310_set_tunable,
+ .remove = mv3310_remove,
+ .set_loopback = genphy_c45_loopback,
+ },
{
.phy_id = MARVELL_PHY_ID_88E2110,
.phy_id_mask = MARVELL_PHY_ID_MASK,
@@ -954,7 +1007,8 @@ static struct phy_driver mv3310_drivers[] = {
module_phy_driver(mv3310_drivers);
static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
- { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_88X33X0_MASK },
+ { MARVELL_PHY_ID_88X3340, MARVELL_PHY_ID_88X33X0_MASK },
{ MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK },
{ },
};
diff --git a/include/linux/marvell_phy.h b/include/linux/marvell_phy.h
index 274abd5fbac3..6b11a5411082 100644
--- a/include/linux/marvell_phy.h
+++ b/include/linux/marvell_phy.h
@@ -22,10 +22,14 @@
#define MARVELL_PHY_ID_88E1545 0x01410ea0
#define MARVELL_PHY_ID_88E1548P 0x01410ec0
#define MARVELL_PHY_ID_88E3016 0x01410e60
-#define MARVELL_PHY_ID_88X3310 0x002b09a0
#define MARVELL_PHY_ID_88E2110 0x002b09b0
#define MARVELL_PHY_ID_88X2222 0x01410f10
+/* PHY IDs and mask for Alaska 10G PHYs */
+#define MARVELL_PHY_ID_88X33X0_MASK 0xfffffff8
+#define MARVELL_PHY_ID_88X3310 0x002b09a0
+#define MARVELL_PHY_ID_88X3340 0x002b09a8
+
/* Marvel 88E1111 in Finisar SFP module with modified PHY ID */
#define MARVELL_PHY_ID_88E1111_FINISAR 0x01ff0cc0
From c89f27d4d239d263a8b5abc597a963bb6b15a661 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Wed, 7 Apr 2021 22:22:50 +0200
Subject: [PATCH 12/16] net: phy: marvell10g: fix driver name for mv88e2110
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The driver name "mv88x2110" should be instead "mv88e2110".
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/phy/marvell10g.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index f74dfd993d8b..3c99757f0306 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -988,7 +988,7 @@ static struct phy_driver mv3310_drivers[] = {
{
.phy_id = MARVELL_PHY_ID_88E2110,
.phy_id_mask = MARVELL_PHY_ID_MASK,
- .name = "mv88x2110",
+ .name = "mv88e2110",
.driver_data = &mv2110_type,
.probe = mv3310_probe,
.suspend = mv3310_suspend,
From 53f111cbfac6f2000c604994ddf01d3299d7de6b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Wed, 7 Apr 2021 22:22:51 +0200
Subject: [PATCH 13/16] net: phy: add constants for 2.5G and 5G speed in PCS
speed register
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add constants for 2.5G and 5G speed in PCS speed register into mdio.h.
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
include/uapi/linux/mdio.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h
index 3f302e2523b2..bdf77dffa5a4 100644
--- a/include/uapi/linux/mdio.h
+++ b/include/uapi/linux/mdio.h
@@ -120,6 +120,8 @@
#define MDIO_PMA_SPEED_100 0x0020 /* 100M capable */
#define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */
#define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */
+#define MDIO_PCS_SPEED_2_5G 0x0040 /* 2.5G capable */
+#define MDIO_PCS_SPEED_5G 0x0080 /* 5G capable */
/* Device present registers. */
#define MDIO_DEVS_PRESENT(devad) (1 << (devad))
From 0fca947cbb27ddb28155996e29385b4ddf5d94f3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Wed, 7 Apr 2021 22:22:52 +0200
Subject: [PATCH 14/16] net: phy: marvell10g: differentiate 88E2110 vs 88E2111
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
88E2111 is a variant of 88E2110 which does not support 5 gigabit speeds.
Differentiate these variants via the match_phy_device() method, since
they have the same PHY ID.
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/phy/marvell10g.c | 62 ++++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 3c99757f0306..fcf4db4e5665 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -918,6 +918,14 @@ static void mv2110_init_supported_interfaces(unsigned long *mask)
__set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
}
+static void mv2111_init_supported_interfaces(unsigned long *mask)
+{
+ __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
+ __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
+}
+
static const struct mv3310_chip mv3310_type = {
.init_supported_interfaces = mv3310_init_supported_interfaces,
.get_mactype = mv3310_get_mactype,
@@ -948,6 +956,41 @@ static const struct mv3310_chip mv2110_type = {
#endif
};
+static const struct mv3310_chip mv2111_type = {
+ .init_supported_interfaces = mv2111_init_supported_interfaces,
+ .get_mactype = mv2110_get_mactype,
+ .init_interface = mv2110_init_interface,
+
+#ifdef CONFIG_HWMON
+ .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,
+#endif
+};
+
+static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g)
+{
+ int val;
+
+ if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
+ MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88E2110)
+ return 0;
+
+ val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_SPEED);
+ if (val < 0)
+ return val;
+
+ return !!(val & MDIO_PCS_SPEED_5G) == has_5g;
+}
+
+static int mv2110_match_phy_device(struct phy_device *phydev)
+{
+ return mv211x_match_phy_device(phydev, true);
+}
+
+static int mv2111_match_phy_device(struct phy_device *phydev)
+{
+ return mv211x_match_phy_device(phydev, false);
+}
+
static struct phy_driver mv3310_drivers[] = {
{
.phy_id = MARVELL_PHY_ID_88X3310,
@@ -988,6 +1031,7 @@ static struct phy_driver mv3310_drivers[] = {
{
.phy_id = MARVELL_PHY_ID_88E2110,
.phy_id_mask = MARVELL_PHY_ID_MASK,
+ .match_phy_device = mv2110_match_phy_device,
.name = "mv88e2110",
.driver_data = &mv2110_type,
.probe = mv3310_probe,
@@ -1002,6 +1046,24 @@ static struct phy_driver mv3310_drivers[] = {
.remove = mv3310_remove,
.set_loopback = genphy_c45_loopback,
},
+ {
+ .phy_id = MARVELL_PHY_ID_88E2110,
+ .phy_id_mask = MARVELL_PHY_ID_MASK,
+ .match_phy_device = mv2111_match_phy_device,
+ .name = "mv88e2111",
+ .driver_data = &mv2111_type,
+ .probe = mv3310_probe,
+ .suspend = mv3310_suspend,
+ .resume = mv3310_resume,
+ .config_init = mv3310_config_init,
+ .config_aneg = mv3310_config_aneg,
+ .aneg_done = mv3310_aneg_done,
+ .read_status = mv3310_read_status,
+ .get_tunable = mv3310_get_tunable,
+ .set_tunable = mv3310_set_tunable,
+ .remove = mv3310_remove,
+ .set_loopback = genphy_c45_loopback,
+ },
};
module_phy_driver(mv3310_drivers);
From c7dce05e63ebc238ad941796d2ca0a90b5902ad3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Wed, 7 Apr 2021 22:22:53 +0200
Subject: [PATCH 15/16] net: phy: marvell10g: change module description
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This module supports not only Alaska X, but also Alaska M.
Change module description appropriately.
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/phy/marvell10g.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index fcf4db4e5665..bbbc6ac8fa82 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -1075,5 +1075,5 @@ static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
{ },
};
MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
-MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)");
+MODULE_DESCRIPTION("Marvell Alaska X/M multi-gigabit Ethernet PHY driver");
MODULE_LICENSE("GPL");
From 9187b6cfe7fcc6f2f5330e82768652bc4931ffb3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Wed, 7 Apr 2021 22:22:54 +0200
Subject: [PATCH 16/16] MAINTAINERS: add myself as maintainer of marvell10g
driver
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add myself as maintainer of the marvell10g ethernet PHY driver, in
addition to Russell King.
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 217c7470bfa9..3ea9539821b5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10695,6 +10695,7 @@ F: include/linux/mv643xx.h
MARVELL MV88X3310 PHY DRIVER
M: Russell King <linux@armlinux.org.uk>
+M: Marek Behun <marek.behun@nic.cz>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/phy/marvell10g.c