tools headers x86 cpufeatures: Sync with the kernel sources
To pick the changes from:3d8f61bf8b("x86: KVM: Add common feature flag for AMD's PSFD")3763bf5802("x86/cpufeatures: Redefine synthetic virtual NMI bit as AMD's "real" vNMI")6449dcb0ca("x86: CPUID and CR3/CR4 flags for Linear Address Masking")be8de49bea("x86/speculation: Identify processors vulnerable to SMT RSB predictions")e7862eda30("x86/cpu: Support AMD Automatic IBRS")faabfcb194("x86/cpu, kvm: Add the SMM_CTL MSR not present feature")5b909d4ae5("x86/cpu, kvm: Add the Null Selector Clears Base feature")84168ae786("x86/cpu, kvm: Move X86_FEATURE_LFENCE_RDTSC to its native leaf")a9dc9ec5a1("x86/cpu, kvm: Add the NO_NESTED_DATA_BP feature")f8df91e73a("x86/cpufeatures: Add macros for Intel's new fast rep string features")78335aac61("x86/cpufeatures: Add Bandwidth Monitoring Event Configuration feature flag")f334f723a6("x86/cpufeatures: Add Slow Memory Bandwidth Allocation feature flag")a018d2e3d4("x86/cpufeatures: Add Architectural PerfMon Extension bit") This causes these perf files to be rebuilt and brings some X86_FEATURE that will be used when updating the copies of tools/arch/x86/lib/mem{cpy,set}_64.S with the kernel sources: CC /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o CC /tmp/build/perf/bench/mem-memset-x86-64-asm.o And addresses this perf build warning: Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h' diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h Cc: Borislav Petkov (AMD) <bp@alien8.de> Cc: Kim Phillips <kim.phillips@amd.com> Cc: Jim Mattson <jmattson@google.com> Cc: Babu Moger <babu.moger@amd.com> Cc: Ingo Molnar <mingo@kernel.org> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Sean Christopherson <seanjc@google.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Link: https://lore.kernel.org/lkml/ZGTTw642q8mWgv2Y@kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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Arnaldo Carvalho de Melo
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9bc83d6e38
@ -97,7 +97,7 @@
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#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */
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#define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */
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#define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* AMD Last Branch Record Extension Version 2 */
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#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */
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/* FREE, was #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) "" LFENCE synchronizes RDTSC */
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#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */
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#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
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#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */
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@ -226,10 +226,9 @@
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/* Virtualization flags: Linux defined, word 8 */
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#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
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#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */
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#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */
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#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */
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#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */
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#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 1) /* Intel FlexPriority */
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#define X86_FEATURE_EPT ( 8*32+ 2) /* Intel Extended Page Table */
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#define X86_FEATURE_VPID ( 8*32+ 3) /* Intel Virtual Processor ID */
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#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer VMMCALL to VMCALL */
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#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */
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@ -307,14 +306,21 @@
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#define X86_FEATURE_SGX_EDECCSSA (11*32+18) /* "" SGX EDECCSSA user leaf function */
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#define X86_FEATURE_CALL_DEPTH (11*32+19) /* "" Call depth tracking for RSB stuffing */
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#define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */
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#define X86_FEATURE_SMBA (11*32+21) /* "" Slow Memory Bandwidth Allocation */
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#define X86_FEATURE_BMEC (11*32+22) /* "" Bandwidth Monitoring Event Configuration */
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/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
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#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
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#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
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#define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instructions */
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#define X86_FEATURE_ARCH_PERFMON_EXT (12*32+ 8) /* "" Intel Architectural PerfMon Extension */
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#define X86_FEATURE_FZRM (12*32+10) /* "" Fast zero-length REP MOVSB */
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#define X86_FEATURE_FSRS (12*32+11) /* "" Fast short REP STOSB */
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#define X86_FEATURE_FSRC (12*32+12) /* "" Fast short REP {CMPSB,SCASB} */
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#define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */
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#define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */
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#define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */
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#define X86_FEATURE_LAM (12*32+26) /* Linear Address Masking */
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/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
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#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
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@ -331,6 +337,7 @@
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#define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */
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#define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
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#define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */
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#define X86_FEATURE_AMD_PSFD (13*32+28) /* "" Predictive Store Forwarding Disable */
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#define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */
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#define X86_FEATURE_BRS (13*32+31) /* Branch Sampling available */
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@ -363,6 +370,7 @@
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#define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */
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#define X86_FEATURE_X2AVIC (15*32+18) /* Virtual x2apic */
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#define X86_FEATURE_V_SPEC_CTRL (15*32+20) /* Virtual SPEC_CTRL */
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#define X86_FEATURE_VNMI (15*32+25) /* Virtual NMI */
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#define X86_FEATURE_SVME_ADDR_CHK (15*32+28) /* "" SVME addr check */
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
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@ -427,6 +435,13 @@
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#define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */
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#define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */
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/* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */
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#define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" No Nested Data Breakpoints */
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#define X86_FEATURE_LFENCE_RDTSC (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */
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#define X86_FEATURE_NULL_SEL_CLR_BASE (20*32+ 6) /* "" Null Selector Clears Base */
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#define X86_FEATURE_AUTOIBRS (20*32+ 8) /* "" Automatic IBRS */
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#define X86_FEATURE_NO_SMM_CTL_MSR (20*32+ 9) /* "" SMM_CTL MSR is not present */
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/*
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* BUG word(s)
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*/
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@ -467,5 +482,6 @@
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#define X86_BUG_MMIO_UNKNOWN X86_BUG(26) /* CPU is too old and its MMIO Stale Data status is unknown */
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#define X86_BUG_RETBLEED X86_BUG(27) /* CPU is affected by RETBleed */
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#define X86_BUG_EIBRS_PBRSB X86_BUG(28) /* EIBRS is vulnerable to Post Barrier RSB Predictions */
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#define X86_BUG_SMT_RSB X86_BUG(29) /* CPU is vulnerable to Cross-Thread Return Address Predictions */
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#endif /* _ASM_X86_CPUFEATURES_H */
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