clk: renesas: Updates for v6.9 (take two)
- Add Ethernet, SDHI, DMA, and HyperFLASH/QSPI (RPC-IF) clocks on
R-Car V4M,
- Miscellaneous fixes and improvements.
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Merge tag 'renesas-clk-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull more Renesas clk driver updates from Geert Uytterhoeven:
- Add Ethernet, SDHI, DMA, and HyperFLASH/QSPI (RPC-IF) clocks on
R-Car V4M
- Miscellaneous fixes and improvements
* tag 'renesas-clk-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a779h0: Add RPC-IF clock
clk: renesas: r8a779h0: Add SYS-DMAC clocks
clk: renesas: r8a779h0: Add SDHI clock
clk: renesas: r8a779h0: Add EtherAVB clocks
clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable
clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 mux
clk: renesas: r8a779f0: Correct PFC/GPIO parent clock
clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks
This commit is contained in:
Stephen Boyd
commit
9bd5726ffb
@ -161,7 +161,7 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
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DEF_MOD("cmt1", 911, R8A779F0_CLK_R),
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DEF_MOD("cmt2", 912, R8A779F0_CLK_R),
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DEF_MOD("cmt3", 913, R8A779F0_CLK_R),
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DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M),
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DEF_MOD("pfc0", 915, R8A779F0_CLK_CPEX),
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DEF_MOD("tsc", 919, R8A779F0_CLK_CL16M),
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DEF_MOD("rswitch2", 1505, R8A779F0_CLK_RSW2),
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DEF_MOD("ether-serdes", 1506, R8A779F0_CLK_S0D2_HSC),
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@ -22,7 +22,7 @@
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R8A779G0_CLK_R,
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LAST_DT_CORE_CLK = R8A779G0_CLK_CP,
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/* External Input Clocks */
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CLK_EXTAL,
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@ -141,6 +141,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
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DEF_FIXED("svd2_vip", R8A779G0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1),
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DEF_FIXED("cbfusa", R8A779G0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
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DEF_FIXED("cpex", R8A779G0_CLK_CPEX, CLK_EXTAL, 2, 1),
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DEF_FIXED("cp", R8A779G0_CLK_CP, CLK_EXTAL, 2, 1),
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DEF_FIXED("viobus", R8A779G0_CLK_VIOBUS, CLK_VIO, 1, 1),
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DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1),
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DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
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@ -232,10 +233,10 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
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DEF_MOD("cmt1", 911, R8A779G0_CLK_R),
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DEF_MOD("cmt2", 912, R8A779G0_CLK_R),
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DEF_MOD("cmt3", 913, R8A779G0_CLK_R),
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DEF_MOD("pfc0", 915, R8A779G0_CLK_CL16M),
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DEF_MOD("pfc1", 916, R8A779G0_CLK_CL16M),
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DEF_MOD("pfc2", 917, R8A779G0_CLK_CL16M),
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DEF_MOD("pfc3", 918, R8A779G0_CLK_CL16M),
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DEF_MOD("pfc0", 915, R8A779G0_CLK_CP),
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DEF_MOD("pfc1", 916, R8A779G0_CLK_CP),
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DEF_MOD("pfc2", 917, R8A779G0_CLK_CP),
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DEF_MOD("pfc3", 918, R8A779G0_CLK_CP),
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DEF_MOD("tsc", 919, R8A779G0_CLK_CL16M),
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DEF_MOD("tsn", 2723, R8A779G0_CLK_S0D4_HSC),
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DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),
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@ -173,6 +173,9 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = {
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};
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static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
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DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC),
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DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC),
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DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC),
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DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1),
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DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1),
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DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1),
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@ -181,6 +184,10 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
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DEF_MOD("i2c1", 519, R8A779H0_CLK_S0D6_PER),
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DEF_MOD("i2c2", 520, R8A779H0_CLK_S0D6_PER),
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DEF_MOD("i2c3", 521, R8A779H0_CLK_S0D6_PER),
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DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2),
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DEF_MOD("sdhi0", 706, R8A779H0_CLK_SD0),
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DEF_MOD("sydm1", 709, R8A779H0_CLK_S0D6_PER),
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DEF_MOD("sydm2", 710, R8A779H0_CLK_S0D6_PER),
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DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R),
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DEF_MOD("pfc0", 915, R8A779H0_CLK_CP),
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DEF_MOD("pfc1", 916, R8A779H0_CLK_CP),
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@ -88,7 +88,7 @@ static const struct clk_div_table dtable_1_32[] = {
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/* Mux clock tables */
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static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
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static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
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static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
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static const char * const sel_sdhi[] = { ".clk_533", ".clk_400", ".clk_266" };
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static const u32 mtable_sdhi[] = { 1, 2, 3 };
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@ -137,9 +137,9 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
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DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2),
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DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
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DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
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DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi,
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DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi,
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mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
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DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, SEL_SDHI0_STS, sel_shdi,
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DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, SEL_SDHI1_STS, sel_sdhi,
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mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
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DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4),
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DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4),
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@ -106,7 +106,7 @@ static const struct clk_div_table dtable_16_128[] = {
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static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
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static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" };
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static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
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static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
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static const char * const sel_sdhi[] = { ".clk_533", ".clk_400", ".clk_266" };
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static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
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static const u32 mtable_sdhi[] = { 1, 2, 3 };
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@ -176,9 +176,9 @@ static const struct {
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DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, sel_pll6_2),
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DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
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DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
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DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi,
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DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi,
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mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
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DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, SEL_SDHI0_STS, sel_shdi,
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DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, SEL_SDHI1_STS, sel_sdhi,
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mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
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DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
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DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
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@ -86,5 +86,6 @@
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#define R8A779G0_CLK_CPEX 74
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#define R8A779G0_CLK_CBFUSA 75
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#define R8A779G0_CLK_R 76
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#define R8A779G0_CLK_CP 77
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#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */
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