From 9bddebf1f0f6e7a8a6418dfc14fdaa6233ba0524 Mon Sep 17 00:00:00 2001 From: Anusha Srivatsa Date: Thu, 23 Mar 2023 15:46:51 -0700 Subject: [PATCH] drm/xe: Load HuC on Alderlake S Alderlake S uses TGL HuC. Signed-off-by: Anusha Srivatsa Reviewed-by: Lucas De Marchi Signed-off-by: Lucas De Marchi Link: https://lore.kernel.org/r/20230323224651.1187366-3-lucas.demarchi@intel.com Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/xe_uc_fw.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c index f3e4e3774d68..5c3789f67049 100644 --- a/drivers/gpu/drm/xe/xe_uc_fw.c +++ b/drivers/gpu/drm/xe/xe_uc_fw.c @@ -51,6 +51,7 @@ static struct xe_device *uc_fw_to_xe(struct xe_uc_fw *uc_fw) fw_def(TIGERLAKE, 0, guc_def(tgl, 70, 5, 2)) #define XE_HUC_FIRMWARE_DEFS(fw_def, huc_def, huc_ver) \ + fw_def(ALDERLAKE_S, 0, huc_def(tgl)) \ fw_def(DG1, 0, huc_def(dg1)) \ fw_def(TIGERLAKE, 0, huc_def(tgl))