drm/i915/guc: Move GuC core definitions into dedicated files
Move GuC core definitions into dedicated files as we want to keep GuC specific code in separated files. v2: move all functions in single patch (Joonas) fix old checkpatch issues (Sagar) v3: rebased Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> #1 Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171004181343.66348-4-michal.wajdeczko@intel.com
This commit is contained in:
parent
9f436c46ea
commit
9bf384c5f2
drivers/gpu/drm/i915
@ -60,6 +60,7 @@ i915-y += i915_cmd_parser.o \
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# general-purpose microcontroller (GuC) support
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# general-purpose microcontroller (GuC) support
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i915-y += intel_uc.o \
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i915-y += intel_uc.o \
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intel_uc_fw.o \
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intel_uc_fw.o \
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intel_guc.o \
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intel_guc_ct.o \
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intel_guc_ct.o \
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intel_guc_log.o \
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intel_guc_log.o \
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intel_guc_loader.o \
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intel_guc_loader.o \
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@ -644,48 +644,6 @@ static void i915_guc_irq_handler(unsigned long data)
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* path of i915_guc_submit() above.
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* path of i915_guc_submit() above.
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*/
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*/
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/**
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* intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
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* @guc: the guc
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* @size: size of area to allocate (both virtual space and memory)
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*
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* This is a wrapper to create an object for use with the GuC. In order to
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* use it inside the GuC, an object needs to be pinned lifetime, so we allocate
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* both some backing storage and a range inside the Global GTT. We must pin
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* it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
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* range is reserved inside GuC.
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*
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* Return: A i915_vma if successful, otherwise an ERR_PTR.
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*/
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struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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int ret;
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obj = i915_gem_object_create(dev_priv, size);
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if (IS_ERR(obj))
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return ERR_CAST(obj);
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vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
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if (IS_ERR(vma))
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goto err;
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ret = i915_vma_pin(vma, 0, PAGE_SIZE,
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PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
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if (ret) {
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vma = ERR_PTR(ret);
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goto err;
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}
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return vma;
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err:
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i915_gem_object_put(obj);
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return vma;
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}
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/* Check that a doorbell register is in the expected state */
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/* Check that a doorbell register is in the expected state */
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static bool doorbell_ok(struct intel_guc *guc, u16 db_id)
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static bool doorbell_ok(struct intel_guc *guc, u16 db_id)
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{
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{
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@ -1213,55 +1171,3 @@ void i915_guc_submission_disable(struct drm_i915_private *dev_priv)
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guc_client_free(guc->execbuf_client);
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guc_client_free(guc->execbuf_client);
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guc->execbuf_client = NULL;
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guc->execbuf_client = NULL;
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}
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}
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/**
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* intel_guc_suspend() - notify GuC entering suspend state
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* @dev_priv: i915 device private
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*/
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int intel_guc_suspend(struct drm_i915_private *dev_priv)
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{
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struct intel_guc *guc = &dev_priv->guc;
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struct i915_gem_context *ctx;
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u32 data[3];
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if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
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return 0;
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gen9_disable_guc_interrupts(dev_priv);
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ctx = dev_priv->kernel_context;
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data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
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/* any value greater than GUC_POWER_D0 */
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data[1] = GUC_POWER_D1;
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/* first page is shared data with GuC */
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data[2] = guc_ggtt_offset(ctx->engine[RCS].state) + LRC_GUCSHR_PN * PAGE_SIZE;
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return intel_guc_send(guc, data, ARRAY_SIZE(data));
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}
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/**
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* intel_guc_resume() - notify GuC resuming from suspend state
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* @dev_priv: i915 device private
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*/
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int intel_guc_resume(struct drm_i915_private *dev_priv)
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{
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struct intel_guc *guc = &dev_priv->guc;
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struct i915_gem_context *ctx;
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u32 data[3];
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if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
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return 0;
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if (i915_modparams.guc_log_level >= 0)
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gen9_enable_guc_interrupts(dev_priv);
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ctx = dev_priv->kernel_context;
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data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
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data[1] = GUC_POWER_D0;
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/* first page is shared data with GuC */
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data[2] = guc_ggtt_offset(ctx->engine[RCS].state) + LRC_GUCSHR_PN * PAGE_SIZE;
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return intel_guc_send(guc, data, ARRAY_SIZE(data));
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}
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264
drivers/gpu/drm/i915/intel_guc.c
Normal file
264
drivers/gpu/drm/i915/intel_guc.c
Normal file
@ -0,0 +1,264 @@
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/*
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* Copyright © 2014-2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "intel_guc.h"
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#include "i915_drv.h"
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static void gen8_guc_raise_irq(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
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}
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static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
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{
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GEM_BUG_ON(!guc->send_regs.base);
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GEM_BUG_ON(!guc->send_regs.count);
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GEM_BUG_ON(i >= guc->send_regs.count);
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return _MMIO(guc->send_regs.base + 4 * i);
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}
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void intel_guc_init_send_regs(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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enum forcewake_domains fw_domains = 0;
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unsigned int i;
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guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
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guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
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for (i = 0; i < guc->send_regs.count; i++) {
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fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
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guc_send_reg(guc, i),
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FW_REG_READ | FW_REG_WRITE);
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}
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guc->send_regs.fw_domains = fw_domains;
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}
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void intel_guc_init_early(struct intel_guc *guc)
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{
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intel_guc_ct_init_early(&guc->ct);
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mutex_init(&guc->send_mutex);
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guc->send = intel_guc_send_nop;
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guc->notify = gen8_guc_raise_irq;
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}
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int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
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{
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WARN(1, "Unexpected send: action=%#x\n", *action);
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return -ENODEV;
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}
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/*
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* This function implements the MMIO based host to GuC interface.
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*/
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int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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u32 status;
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int i;
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int ret;
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GEM_BUG_ON(!len);
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GEM_BUG_ON(len > guc->send_regs.count);
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/* If CT is available, we expect to use MMIO only during init/fini */
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GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
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*action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
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*action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
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mutex_lock(&guc->send_mutex);
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intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
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for (i = 0; i < len; i++)
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I915_WRITE(guc_send_reg(guc, i), action[i]);
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POSTING_READ(guc_send_reg(guc, i - 1));
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intel_guc_notify(guc);
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/*
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* No GuC command should ever take longer than 10ms.
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* Fast commands should still complete in 10us.
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*/
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ret = __intel_wait_for_register_fw(dev_priv,
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guc_send_reg(guc, 0),
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INTEL_GUC_RECV_MASK,
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INTEL_GUC_RECV_MASK,
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10, 10, &status);
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if (status != INTEL_GUC_STATUS_SUCCESS) {
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/*
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* Either the GuC explicitly returned an error (which
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* we convert to -EIO here) or no response at all was
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* received within the timeout limit (-ETIMEDOUT)
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*/
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if (ret != -ETIMEDOUT)
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ret = -EIO;
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DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
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" ret=%d status=0x%08X response=0x%08X\n",
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action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
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}
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intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
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mutex_unlock(&guc->send_mutex);
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return ret;
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}
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int intel_guc_sample_forcewake(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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u32 action[2];
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action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
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/* WaRsDisableCoarsePowerGating:skl,bxt */
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if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
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action[1] = 0;
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else
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/* bit 0 and 1 are for Render and Media domain separately */
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action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
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return intel_guc_send(guc, action, ARRAY_SIZE(action));
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}
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/**
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* intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
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* @guc: intel_guc structure
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* @rsa_offset: rsa offset w.r.t ggtt base of huc vma
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*
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* Triggers a HuC firmware authentication request to the GuC via intel_guc_send
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* INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
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* intel_huc_auth().
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*
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* Return: non-zero code on error
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*/
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int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
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{
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u32 action[] = {
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INTEL_GUC_ACTION_AUTHENTICATE_HUC,
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rsa_offset
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};
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return intel_guc_send(guc, action, ARRAY_SIZE(action));
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}
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/**
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* intel_guc_suspend() - notify GuC entering suspend state
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* @dev_priv: i915 device private
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*/
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int intel_guc_suspend(struct drm_i915_private *dev_priv)
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{
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struct intel_guc *guc = &dev_priv->guc;
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struct i915_gem_context *ctx;
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u32 data[3];
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if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
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return 0;
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gen9_disable_guc_interrupts(dev_priv);
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ctx = dev_priv->kernel_context;
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data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
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/* any value greater than GUC_POWER_D0 */
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data[1] = GUC_POWER_D1;
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/* first page is shared data with GuC */
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data[2] = guc_ggtt_offset(ctx->engine[RCS].state) +
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LRC_GUCSHR_PN * PAGE_SIZE;
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return intel_guc_send(guc, data, ARRAY_SIZE(data));
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}
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/**
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* intel_guc_resume() - notify GuC resuming from suspend state
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* @dev_priv: i915 device private
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*/
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int intel_guc_resume(struct drm_i915_private *dev_priv)
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{
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struct intel_guc *guc = &dev_priv->guc;
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struct i915_gem_context *ctx;
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u32 data[3];
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if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
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return 0;
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if (i915_modparams.guc_log_level >= 0)
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gen9_enable_guc_interrupts(dev_priv);
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ctx = dev_priv->kernel_context;
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data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
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data[1] = GUC_POWER_D0;
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/* first page is shared data with GuC */
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data[2] = guc_ggtt_offset(ctx->engine[RCS].state) +
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LRC_GUCSHR_PN * PAGE_SIZE;
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return intel_guc_send(guc, data, ARRAY_SIZE(data));
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}
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/**
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* intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
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* @guc: the guc
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||||||
|
* @size: size of area to allocate (both virtual space and memory)
|
||||||
|
*
|
||||||
|
* This is a wrapper to create an object for use with the GuC. In order to
|
||||||
|
* use it inside the GuC, an object needs to be pinned lifetime, so we allocate
|
||||||
|
* both some backing storage and a range inside the Global GTT. We must pin
|
||||||
|
* it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
|
||||||
|
* range is reserved inside GuC.
|
||||||
|
*
|
||||||
|
* Return: A i915_vma if successful, otherwise an ERR_PTR.
|
||||||
|
*/
|
||||||
|
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
|
||||||
|
{
|
||||||
|
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
||||||
|
struct drm_i915_gem_object *obj;
|
||||||
|
struct i915_vma *vma;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
obj = i915_gem_object_create(dev_priv, size);
|
||||||
|
if (IS_ERR(obj))
|
||||||
|
return ERR_CAST(obj);
|
||||||
|
|
||||||
|
vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
|
||||||
|
if (IS_ERR(vma))
|
||||||
|
goto err;
|
||||||
|
|
||||||
|
ret = i915_vma_pin(vma, 0, PAGE_SIZE,
|
||||||
|
PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
|
||||||
|
if (ret) {
|
||||||
|
vma = ERR_PTR(ret);
|
||||||
|
goto err;
|
||||||
|
}
|
||||||
|
|
||||||
|
return vma;
|
||||||
|
|
||||||
|
err:
|
||||||
|
i915_gem_object_put(obj);
|
||||||
|
return vma;
|
||||||
|
}
|
109
drivers/gpu/drm/i915/intel_guc.h
Normal file
109
drivers/gpu/drm/i915/intel_guc.h
Normal file
@ -0,0 +1,109 @@
|
|||||||
|
/*
|
||||||
|
* Copyright © 2014-2017 Intel Corporation
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
|
* to deal in the Software without restriction, including without limitation
|
||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice (including the next
|
||||||
|
* paragraph) shall be included in all copies or substantial portions of the
|
||||||
|
* Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||||
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||||
|
* IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _INTEL_GUC_H_
|
||||||
|
#define _INTEL_GUC_H_
|
||||||
|
|
||||||
|
#include "intel_uncore.h"
|
||||||
|
#include "intel_guc_fwif.h"
|
||||||
|
#include "intel_guc_ct.h"
|
||||||
|
#include "intel_guc_log.h"
|
||||||
|
#include "intel_uc_fw.h"
|
||||||
|
#include "i915_guc_reg.h"
|
||||||
|
#include "i915_vma.h"
|
||||||
|
|
||||||
|
struct intel_guc {
|
||||||
|
struct intel_uc_fw fw;
|
||||||
|
struct intel_guc_log log;
|
||||||
|
struct intel_guc_ct ct;
|
||||||
|
|
||||||
|
/* Log snapshot if GuC errors during load */
|
||||||
|
struct drm_i915_gem_object *load_err_log;
|
||||||
|
|
||||||
|
/* intel_guc_recv interrupt related state */
|
||||||
|
bool interrupts_enabled;
|
||||||
|
|
||||||
|
struct i915_vma *ads_vma;
|
||||||
|
struct i915_vma *stage_desc_pool;
|
||||||
|
void *stage_desc_pool_vaddr;
|
||||||
|
struct ida stage_ids;
|
||||||
|
|
||||||
|
struct i915_guc_client *execbuf_client;
|
||||||
|
|
||||||
|
DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
|
||||||
|
uint32_t db_cacheline; /* Cyclic counter mod pagesize */
|
||||||
|
|
||||||
|
/* GuC's FW specific registers used in MMIO send */
|
||||||
|
struct {
|
||||||
|
u32 base;
|
||||||
|
unsigned int count;
|
||||||
|
enum forcewake_domains fw_domains;
|
||||||
|
} send_regs;
|
||||||
|
|
||||||
|
/* To serialize the intel_guc_send actions */
|
||||||
|
struct mutex send_mutex;
|
||||||
|
|
||||||
|
/* GuC's FW specific send function */
|
||||||
|
int (*send)(struct intel_guc *guc, const u32 *data, u32 len);
|
||||||
|
|
||||||
|
/* GuC's FW specific notify function */
|
||||||
|
void (*notify)(struct intel_guc *guc);
|
||||||
|
};
|
||||||
|
|
||||||
|
static
|
||||||
|
inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
|
||||||
|
{
|
||||||
|
return guc->send(guc, action, len);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void intel_guc_notify(struct intel_guc *guc)
|
||||||
|
{
|
||||||
|
guc->notify(guc);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline u32 guc_ggtt_offset(struct i915_vma *vma)
|
||||||
|
{
|
||||||
|
u32 offset = i915_ggtt_offset(vma);
|
||||||
|
|
||||||
|
GEM_BUG_ON(offset < GUC_WOPCM_TOP);
|
||||||
|
GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
|
||||||
|
|
||||||
|
return offset;
|
||||||
|
}
|
||||||
|
|
||||||
|
void intel_guc_init_early(struct intel_guc *guc);
|
||||||
|
void intel_guc_init_send_regs(struct intel_guc *guc);
|
||||||
|
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
|
||||||
|
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
|
||||||
|
int intel_guc_sample_forcewake(struct intel_guc *guc);
|
||||||
|
int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
|
||||||
|
int intel_guc_suspend(struct drm_i915_private *dev_priv);
|
||||||
|
int intel_guc_resume(struct drm_i915_private *dev_priv);
|
||||||
|
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
|
||||||
|
|
||||||
|
int intel_guc_select_fw(struct intel_guc *guc);
|
||||||
|
int intel_guc_init_hw(struct intel_guc *guc);
|
||||||
|
u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
|
||||||
|
|
||||||
|
#endif
|
@ -82,25 +82,9 @@ void intel_uc_sanitize_options(struct drm_i915_private *dev_priv)
|
|||||||
i915_modparams.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
|
i915_modparams.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void gen8_guc_raise_irq(struct intel_guc *guc)
|
|
||||||
{
|
|
||||||
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
|
||||||
|
|
||||||
I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void guc_init_early(struct intel_guc *guc)
|
|
||||||
{
|
|
||||||
intel_guc_ct_init_early(&guc->ct);
|
|
||||||
|
|
||||||
mutex_init(&guc->send_mutex);
|
|
||||||
guc->send = intel_guc_send_nop;
|
|
||||||
guc->notify = gen8_guc_raise_irq;
|
|
||||||
}
|
|
||||||
|
|
||||||
void intel_uc_init_early(struct drm_i915_private *dev_priv)
|
void intel_uc_init_early(struct drm_i915_private *dev_priv)
|
||||||
{
|
{
|
||||||
guc_init_early(&dev_priv->guc);
|
intel_guc_init_early(&dev_priv->guc);
|
||||||
}
|
}
|
||||||
|
|
||||||
void intel_uc_init_fw(struct drm_i915_private *dev_priv)
|
void intel_uc_init_fw(struct drm_i915_private *dev_priv)
|
||||||
@ -115,32 +99,6 @@ void intel_uc_fini_fw(struct drm_i915_private *dev_priv)
|
|||||||
intel_uc_fw_fini(&dev_priv->huc.fw);
|
intel_uc_fw_fini(&dev_priv->huc.fw);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
|
|
||||||
{
|
|
||||||
GEM_BUG_ON(!guc->send_regs.base);
|
|
||||||
GEM_BUG_ON(!guc->send_regs.count);
|
|
||||||
GEM_BUG_ON(i >= guc->send_regs.count);
|
|
||||||
|
|
||||||
return _MMIO(guc->send_regs.base + 4 * i);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void guc_init_send_regs(struct intel_guc *guc)
|
|
||||||
{
|
|
||||||
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
|
||||||
enum forcewake_domains fw_domains = 0;
|
|
||||||
unsigned int i;
|
|
||||||
|
|
||||||
guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
|
|
||||||
guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
|
|
||||||
|
|
||||||
for (i = 0; i < guc->send_regs.count; i++) {
|
|
||||||
fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
|
|
||||||
guc_send_reg(guc, i),
|
|
||||||
FW_REG_READ | FW_REG_WRITE);
|
|
||||||
}
|
|
||||||
guc->send_regs.fw_domains = fw_domains;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* intel_uc_init_mmio - setup uC MMIO access
|
* intel_uc_init_mmio - setup uC MMIO access
|
||||||
*
|
*
|
||||||
@ -151,7 +109,7 @@ static void guc_init_send_regs(struct intel_guc *guc)
|
|||||||
*/
|
*/
|
||||||
void intel_uc_init_mmio(struct drm_i915_private *dev_priv)
|
void intel_uc_init_mmio(struct drm_i915_private *dev_priv)
|
||||||
{
|
{
|
||||||
guc_init_send_regs(&dev_priv->guc);
|
intel_guc_init_send_regs(&dev_priv->guc);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void guc_capture_load_err_log(struct intel_guc *guc)
|
static void guc_capture_load_err_log(struct intel_guc *guc)
|
||||||
@ -192,27 +150,6 @@ static void guc_disable_communication(struct intel_guc *guc)
|
|||||||
guc->send = intel_guc_send_nop;
|
guc->send = intel_guc_send_nop;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
|
||||||
* intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
|
|
||||||
* @guc: intel_guc structure
|
|
||||||
* @rsa_offset: rsa offset w.r.t ggtt base of huc vma
|
|
||||||
*
|
|
||||||
* Triggers a HuC firmware authentication request to the GuC via intel_guc_send
|
|
||||||
* INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
|
|
||||||
* intel_huc_auth().
|
|
||||||
*
|
|
||||||
* Return: non-zero code on error
|
|
||||||
*/
|
|
||||||
int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
|
|
||||||
{
|
|
||||||
u32 action[] = {
|
|
||||||
INTEL_GUC_ACTION_AUTHENTICATE_HUC,
|
|
||||||
rsa_offset
|
|
||||||
};
|
|
||||||
|
|
||||||
return intel_guc_send(guc, action, ARRAY_SIZE(action));
|
|
||||||
}
|
|
||||||
|
|
||||||
int intel_uc_init_hw(struct drm_i915_private *dev_priv)
|
int intel_uc_init_hw(struct drm_i915_private *dev_priv)
|
||||||
{
|
{
|
||||||
struct intel_guc *guc = &dev_priv->guc;
|
struct intel_guc *guc = &dev_priv->guc;
|
||||||
@ -344,82 +281,3 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
|
|||||||
|
|
||||||
i915_ggtt_disable_guc(dev_priv);
|
i915_ggtt_disable_guc(dev_priv);
|
||||||
}
|
}
|
||||||
|
|
||||||
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
|
|
||||||
{
|
|
||||||
WARN(1, "Unexpected send: action=%#x\n", *action);
|
|
||||||
return -ENODEV;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This function implements the MMIO based host to GuC interface.
|
|
||||||
*/
|
|
||||||
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
|
|
||||||
{
|
|
||||||
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
|
||||||
u32 status;
|
|
||||||
int i;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
GEM_BUG_ON(!len);
|
|
||||||
GEM_BUG_ON(len > guc->send_regs.count);
|
|
||||||
|
|
||||||
/* If CT is available, we expect to use MMIO only during init/fini */
|
|
||||||
GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
|
|
||||||
*action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
|
|
||||||
*action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
|
|
||||||
|
|
||||||
mutex_lock(&guc->send_mutex);
|
|
||||||
intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
|
|
||||||
|
|
||||||
for (i = 0; i < len; i++)
|
|
||||||
I915_WRITE(guc_send_reg(guc, i), action[i]);
|
|
||||||
|
|
||||||
POSTING_READ(guc_send_reg(guc, i - 1));
|
|
||||||
|
|
||||||
intel_guc_notify(guc);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* No GuC command should ever take longer than 10ms.
|
|
||||||
* Fast commands should still complete in 10us.
|
|
||||||
*/
|
|
||||||
ret = __intel_wait_for_register_fw(dev_priv,
|
|
||||||
guc_send_reg(guc, 0),
|
|
||||||
INTEL_GUC_RECV_MASK,
|
|
||||||
INTEL_GUC_RECV_MASK,
|
|
||||||
10, 10, &status);
|
|
||||||
if (status != INTEL_GUC_STATUS_SUCCESS) {
|
|
||||||
/*
|
|
||||||
* Either the GuC explicitly returned an error (which
|
|
||||||
* we convert to -EIO here) or no response at all was
|
|
||||||
* received within the timeout limit (-ETIMEDOUT)
|
|
||||||
*/
|
|
||||||
if (ret != -ETIMEDOUT)
|
|
||||||
ret = -EIO;
|
|
||||||
|
|
||||||
DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
|
|
||||||
" ret=%d status=0x%08X response=0x%08X\n",
|
|
||||||
action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
|
|
||||||
}
|
|
||||||
|
|
||||||
intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
|
|
||||||
mutex_unlock(&guc->send_mutex);
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
int intel_guc_sample_forcewake(struct intel_guc *guc)
|
|
||||||
{
|
|
||||||
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
|
||||||
u32 action[2];
|
|
||||||
|
|
||||||
action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
|
|
||||||
/* WaRsDisableCoarsePowerGating:skl,bxt */
|
|
||||||
if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
|
|
||||||
action[1] = 0;
|
|
||||||
else
|
|
||||||
/* bit 0 and 1 are for Render and Media domain separately */
|
|
||||||
action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
|
|
||||||
|
|
||||||
return intel_guc_send(guc, action, ARRAY_SIZE(action));
|
|
||||||
}
|
|
||||||
|
@ -24,54 +24,9 @@
|
|||||||
#ifndef _INTEL_UC_H_
|
#ifndef _INTEL_UC_H_
|
||||||
#define _INTEL_UC_H_
|
#define _INTEL_UC_H_
|
||||||
|
|
||||||
#include "intel_uc_fw.h"
|
#include "intel_guc.h"
|
||||||
#include "intel_guc_fwif.h"
|
|
||||||
#include "i915_guc_reg.h"
|
|
||||||
#include "intel_ringbuffer.h"
|
|
||||||
#include "intel_guc_ct.h"
|
|
||||||
#include "intel_guc_log.h"
|
|
||||||
#include "i915_vma.h"
|
|
||||||
#include "intel_huc.h"
|
#include "intel_huc.h"
|
||||||
|
|
||||||
struct intel_guc {
|
|
||||||
struct intel_uc_fw fw;
|
|
||||||
struct intel_guc_log log;
|
|
||||||
struct intel_guc_ct ct;
|
|
||||||
|
|
||||||
/* Log snapshot if GuC errors during load */
|
|
||||||
struct drm_i915_gem_object *load_err_log;
|
|
||||||
|
|
||||||
/* intel_guc_recv interrupt related state */
|
|
||||||
bool interrupts_enabled;
|
|
||||||
|
|
||||||
struct i915_vma *ads_vma;
|
|
||||||
struct i915_vma *stage_desc_pool;
|
|
||||||
void *stage_desc_pool_vaddr;
|
|
||||||
struct ida stage_ids;
|
|
||||||
|
|
||||||
struct i915_guc_client *execbuf_client;
|
|
||||||
|
|
||||||
DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
|
|
||||||
uint32_t db_cacheline; /* Cyclic counter mod pagesize */
|
|
||||||
|
|
||||||
/* GuC's FW specific registers used in MMIO send */
|
|
||||||
struct {
|
|
||||||
u32 base;
|
|
||||||
unsigned int count;
|
|
||||||
enum forcewake_domains fw_domains;
|
|
||||||
} send_regs;
|
|
||||||
|
|
||||||
/* To serialize the intel_guc_send actions */
|
|
||||||
struct mutex send_mutex;
|
|
||||||
|
|
||||||
/* GuC's FW specific send function */
|
|
||||||
int (*send)(struct intel_guc *guc, const u32 *data, u32 len);
|
|
||||||
|
|
||||||
/* GuC's FW specific notify function */
|
|
||||||
void (*notify)(struct intel_guc *guc);
|
|
||||||
};
|
|
||||||
|
|
||||||
/* intel_uc.c */
|
|
||||||
void intel_uc_sanitize_options(struct drm_i915_private *dev_priv);
|
void intel_uc_sanitize_options(struct drm_i915_private *dev_priv);
|
||||||
void intel_uc_init_early(struct drm_i915_private *dev_priv);
|
void intel_uc_init_early(struct drm_i915_private *dev_priv);
|
||||||
void intel_uc_init_mmio(struct drm_i915_private *dev_priv);
|
void intel_uc_init_mmio(struct drm_i915_private *dev_priv);
|
||||||
@ -79,36 +34,5 @@ void intel_uc_init_fw(struct drm_i915_private *dev_priv);
|
|||||||
void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
|
void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
|
||||||
int intel_uc_init_hw(struct drm_i915_private *dev_priv);
|
int intel_uc_init_hw(struct drm_i915_private *dev_priv);
|
||||||
void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
|
void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
|
||||||
int intel_guc_sample_forcewake(struct intel_guc *guc);
|
|
||||||
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
|
|
||||||
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
|
|
||||||
int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
|
|
||||||
|
|
||||||
static inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
|
|
||||||
{
|
|
||||||
return guc->send(guc, action, len);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void intel_guc_notify(struct intel_guc *guc)
|
|
||||||
{
|
|
||||||
guc->notify(guc);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* intel_guc_loader.c */
|
|
||||||
int intel_guc_select_fw(struct intel_guc *guc);
|
|
||||||
int intel_guc_init_hw(struct intel_guc *guc);
|
|
||||||
int intel_guc_suspend(struct drm_i915_private *dev_priv);
|
|
||||||
int intel_guc_resume(struct drm_i915_private *dev_priv);
|
|
||||||
u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
|
|
||||||
|
|
||||||
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
|
|
||||||
|
|
||||||
static inline u32 guc_ggtt_offset(struct i915_vma *vma)
|
|
||||||
{
|
|
||||||
u32 offset = i915_ggtt_offset(vma);
|
|
||||||
GEM_BUG_ON(offset < GUC_WOPCM_TOP);
|
|
||||||
GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
|
|
||||||
return offset;
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
Loading…
x
Reference in New Issue
Block a user