drm/i915/chv: use vlv_PLL_is_optimal in chv_find_best_dpll
Prepare chv_find_best_dpll to be used for BXT too, where we want to consider the error between target and calculated frequency too when choosing a better PLL configuration. No functional change. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -786,6 +786,16 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
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unsigned int best_error_ppm,
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unsigned int *error_ppm)
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{
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/*
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* For CHV ignore the error and consider only the P value.
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* Prefer a bigger P value based on HW requirements.
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*/
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if (IS_CHERRYVIEW(dev)) {
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*error_ppm = 0;
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return calculated_clock->p > best_clock->p;
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}
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if (WARN_ON_ONCE(!target_freq))
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return false;
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@ -864,11 +874,13 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
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intel_clock_t *best_clock)
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{
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struct drm_device *dev = crtc->base.dev;
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unsigned int best_error_ppm;
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intel_clock_t clock;
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uint64_t m2;
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int found = false;
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memset(best_clock, 0, sizeof(*best_clock));
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best_error_ppm = 1000000;
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/*
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* Based on hardware doc, the n always set to 1, and m1 always
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@ -882,6 +894,7 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
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for (clock.p2 = limit->p2.p2_fast;
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clock.p2 >= limit->p2.p2_slow;
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clock.p2 -= clock.p2 > 10 ? 2 : 1) {
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unsigned int error_ppm;
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clock.p = clock.p1 * clock.p2;
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@ -898,12 +911,13 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
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if (!intel_PLL_is_valid(dev, limit, &clock))
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continue;
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/* based on hardware requirement, prefer bigger p
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*/
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if (clock.p > best_clock->p) {
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*best_clock = clock;
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found = true;
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}
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if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
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best_error_ppm, &error_ppm))
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continue;
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*best_clock = clock;
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best_error_ppm = error_ppm;
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found = true;
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}
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}
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