drm/amdgpu: add the accelerator PCIe class
Add the accelerator PCIe class and match the class in amdgpu for 0x1002 devices of that class. From PCI spec: "PCI Code and ID Assignment, r1.9, sec 1, 1.19" Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> # pci_ids.h Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2044,7 +2044,7 @@ static const struct pci_device_id pciidlist[] = {
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.driver_data = CHIP_IP_DISCOVERY },
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{ PCI_DEVICE(0x1002, PCI_ANY_ID),
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.class = AMD_ACCELERATOR_PROCESSING << 8,
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.class = PCI_CLASS_ACCELERATOR_PROCESSING << 8,
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.class_mask = 0xffffff,
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.driver_data = CHIP_IP_DISCOVERY },
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@ -57,7 +57,7 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev)
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/* enable virtual display */
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if (adev->asic_type != CHIP_ALDEBARAN &&
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adev->asic_type != CHIP_ARCTURUS &&
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((adev->pdev->class >> 8) != AMD_ACCELERATOR_PROCESSING)) {
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((adev->pdev->class >> 8) != PCI_CLASS_ACCELERATOR_PROCESSING)) {
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if (adev->mode_info.num_crtc == 0)
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adev->mode_info.num_crtc = 1;
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adev->enable_virtual_display = true;
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@ -27,7 +27,6 @@
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#define AMD_MAX_USEC_TIMEOUT 1000000 /* 1000 ms */
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#define AMD_ACCELERATOR_PROCESSING 0x1200 /* hardcoded pci class */
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/*
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* Chip flags
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@ -151,6 +151,9 @@
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#define PCI_CLASS_SP_DPIO 0x1100
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#define PCI_CLASS_SP_OTHER 0x1180
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#define PCI_BASE_CLASS_ACCELERATOR 0x12
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#define PCI_CLASS_ACCELERATOR_PROCESSING 0x1200
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#define PCI_CLASS_OTHERS 0xff
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/* Vendors and devices. Sort key: vendor first, device next. */
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