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Merge branch 'r8169-sync-few-functionalities-with-vendor-driver'

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Heiner Kallweit says:

====================
r8169: sync few functionalities with vendor driver

Add few helpers (with names copied from vendor drivers) to make clearer
what the respective code is doing. In addition improve reset preparation
for chips from RTL8168g.
====================

Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2020-05-08 22:42:31 -07:00
commit 9dfff80280
1 changed files with 39 additions and 24 deletions
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63
drivers/net/ethernet/realtek/r8169_main.c
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@ -2494,6 +2494,33 @@ DECLARE_RTL_COND(rtl_txcfg_empty_cond)
return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
}
DECLARE_RTL_COND(rtl_rxtx_empty_cond)
{
return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
}
static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
{
switch (tp->mac_version) {
case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
break;
case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
break;
default:
break;
}
}
static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
{
RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
fsleep(2000);
rtl_wait_txrx_fifo_empty(tp);
}
static void rtl8169_hw_reset(struct rtl8169_private *tp)
{
/* Disable interrupts */
@ -2508,10 +2535,13 @@ static void rtl8169_hw_reset(struct rtl8169_private *tp)
rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
break;
case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
break;
case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
rtl_enable_rxdvgate(tp);
fsleep(2000);
break;
default:
RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
udelay(100);
@ -5055,9 +5085,9 @@ DECLARE_RTL_COND(rtl_link_list_ready_cond)
return RTL_R8(tp, MCU) & LINK_LIST_RDY;
}
DECLARE_RTL_COND(rtl_rxtx_empty_cond)
static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
{
return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
}
static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
@ -5126,49 +5156,34 @@ static int r8169_mdio_register(struct rtl8169_private *tp)
static void rtl_hw_init_8168g(struct rtl8169_private *tp)
{
RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
if (!rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
return;
if (!rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
return;
rtl_enable_rxdvgate(tp);
RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
msleep(1);
RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
if (!rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
return;
r8168g_wait_ll_share_fifo_ready(tp);
r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
r8168g_wait_ll_share_fifo_ready(tp);
}
static void rtl_hw_init_8125(struct rtl8169_private *tp)
{
RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
if (!rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
return;
rtl_enable_rxdvgate(tp);
RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
msleep(1);
RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
if (!rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
return;
r8168g_wait_ll_share_fifo_ready(tp);
r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
r8168g_wait_ll_share_fifo_ready(tp);
}
static void rtl_hw_initialize(struct rtl8169_private *tp)