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net: dsa: rzn1-a5psw: enable management frames for CPU port

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Currently, management frame were discarded before reaching the CPU port due
to a misconfiguration of the MGMT_CONFIG register. Enable them by setting
the correct value in this register in order to correctly receive management
frame and handle STP.

Fixes: 888cdb892b61 ("net: dsa: rzn1-a5psw: add Renesas RZ/N1 advanced 5 port switch driver")
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
Reviewed-by: Piotr Raczynski <piotr.raczynski@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Clément Léger 2023-05-12 09:27:10 +02:00 committed by David S. Miller
parent d80fc101d2
commit 9e4b45f20c
2 changed files with 2 additions and 2 deletions
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2
drivers/net/dsa/rzn1_a5psw.c
View File

@ -673,7 +673,7 @@ static int a5psw_setup(struct dsa_switch *ds)
}
/* Configure management port */
reg = A5PSW_CPU_PORT | A5PSW_MGMT_CFG_DISCARD;
reg = A5PSW_CPU_PORT | A5PSW_MGMT_CFG_ENABLE;
a5psw_reg_writel(a5psw, A5PSW_MGMT_CFG, reg);
/* Set pattern 0 to forward all frame to mgmt port */

2
drivers/net/dsa/rzn1_a5psw.h
View File

@ -36,7 +36,7 @@
#define A5PSW_INPUT_LEARN_BLOCK(p) BIT(p)
#define A5PSW_MGMT_CFG 0x20
#define A5PSW_MGMT_CFG_DISCARD BIT(7)
#define A5PSW_MGMT_CFG_ENABLE BIT(6)
#define A5PSW_MODE_CFG 0x24
#define A5PSW_MODE_STATS_RESET BIT(31)