i.MX clock changes for 5.4:
- Add clock driver for i.MX8MN SoC. - Switch i.MX8MM clock driver to platform driver. - Add API for clk unregister when driver probe fail. - Add Hifi4 DSP related clocks for i.MX8QXP SoC. - Fix Audio PLL setting and parent clock for USB. - Misc i.MX8 clock driver improvements and corrections. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJdYmqKAAoJEFBXWFqHsHzO4roH/jD8tQ0m0oi17oBgrgVUTv63 uBUMlfKeQDOGUM4dp55bqhyEkhGIysYI3mpDPkcglRtqHNYjx8ESQam7vzycKqnU REFud1P5ERpSEhZ50e41L0J2/LyN12xO2zMCsZw1S7xO29OdPUeaS1sNIJx7NOQW hyN+8RJBbwZ8iRyatWAJepoXv9FepTZ2iMPacHRk3Xdq7JnmQGZcowfjThInq5cV nQQBdu7FyWSHj83WWcbTcknTXc5513sPfhn7Sw7jTT4TZ6ZWipKduBoRMEQIDy7d jkAz5Idiim85oJ9Qzq5JwELIa09GC1ieWkr2LToPM/ZuktIlmxMF8+3nV4CpAdg= =qzTi -----END PGP SIGNATURE----- Merge tag 'clk-imx-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx Pull i.MX clock changes from Shawn Guo: - Add clock driver for i.MX8MN SoC - Switch i.MX8MM clock driver to platform driver - Add API for clk unregister when driver probe fail - Add Hifi4 DSP related clocks for i.MX8QXP SoC - Fix Audio PLL setting and parent clock for USB - Misc i.MX8 clock driver improvements and corrections * tag 'clk-imx-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (28 commits) clk: imx: imx8mn: fix audio pll setting clk: imx8mn: Add necessary frequency support for ARM PLL table clk: imx8mn: Add missing rate_count assignment for each PLL structure clk: imx8mn: fix int pll clk gate clk: imx8mn: Add GIC clock clk: imx8mn: Fix incorrect parents clk: imx8mm: Fix incorrect parents clk: imx8mq: Fix sys3 pll references clk: imx8mq: Unregister clks when of_clk_add_provider failed clk: imx8mm: Unregister clks when of_clk_add_provider failed clk: imx8mq: Mark AHB clock as critical clk: imx8mn: Keep uart clocks on for early console clk: imx: Remove unused function statement clk: imx7ulp: Make sure earlycon's clock is enabled clk: imx8mm: Switch to platform driver clk: imx: imx8mm: fix audio pll setting clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m clk: imx8mm: Fix typo of pwm3 clock's mux option #4 clk: imx: Remove unused clk based API clk: imx8mq: set correct parent for usb ctrl clocks ...
This commit is contained in:
Stephen Boyd
commit
9ea67d14a8
112
Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
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112
Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
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@ -0,0 +1,112 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/clock/imx8mn-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8M Nano Clock Control Module Binding
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maintainers:
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- Anson Huang <Anson.Huang@nxp.com>
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description: |
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NXP i.MX8M Nano clock control module is an integrated clock controller, which
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generates and supplies to all modules.
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properties:
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compatible:
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const: fsl,imx8mn-ccm
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reg:
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maxItems: 1
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clocks:
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items:
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- description: 32k osc
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- description: 24m osc
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- description: ext1 clock input
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- description: ext2 clock input
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- description: ext3 clock input
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- description: ext4 clock input
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clock-names:
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items:
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- const: osc_32k
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- const: osc_24m
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- const: clk_ext1
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- const: clk_ext2
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- const: clk_ext3
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- const: clk_ext4
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'#clock-cells':
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const: 1
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description: |
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h
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for the full list of i.MX8M Nano clock IDs.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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examples:
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# Clock Control Module node:
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- |
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clk: clock-controller@30380000 {
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compatible = "fsl,imx8mn-ccm";
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reg = <0x0 0x30380000 0x0 0x10000>;
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#clock-cells = <1>;
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clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>,
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<&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
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clock-names = "osc_32k", "osc_24m", "clk_ext1",
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"clk_ext2", "clk_ext3", "clk_ext4";
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};
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# Required external clocks for Clock Control Module node:
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- |
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osc_32k: clock-osc-32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "osc_32k";
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};
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osc_24m: clock-osc-24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "osc_24m";
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};
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clk_ext1: clock-ext1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext1";
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};
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clk_ext2: clock-ext2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext2";
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};
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clk_ext3: clock-ext3 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext3";
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};
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clk_ext4: clock-ext4 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency= <133000000>;
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clock-output-names = "clk_ext4";
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};
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...
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@ -14,6 +14,12 @@ config CLK_IMX8MM
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help
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Build the driver for i.MX8MM CCM Clock Driver
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config CLK_IMX8MN
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bool "IMX8MN CCM Clock Driver"
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depends on ARCH_MXC && ARM64
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help
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Build the driver for i.MX8MN CCM Clock Driver
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config CLK_IMX8MQ
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bool "IMX8MQ CCM Clock Driver"
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depends on ARCH_MXC && ARM64
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@ -26,6 +26,7 @@ obj-$(CONFIG_MXC_CLK_SCU) += \
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clk-lpcg-scu.o
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obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
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obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o
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obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
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obj-$(CONFIG_CLK_IMX8QXP) += clk-imx8qxp.o clk-imx8qxp-lpcg.o
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@ -42,6 +42,19 @@ static const struct clk_div_table ulp_div_table[] = {
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{ .val = 7, .div = 64, },
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};
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static const int pcc2_uart_clk_ids[] __initconst = {
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IMX7ULP_CLK_LPUART4,
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IMX7ULP_CLK_LPUART5,
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};
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static const int pcc3_uart_clk_ids[] __initconst = {
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IMX7ULP_CLK_LPUART6,
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IMX7ULP_CLK_LPUART7,
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};
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static struct clk **pcc2_uart_clks[ARRAY_SIZE(pcc2_uart_clk_ids) + 1] __initdata;
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static struct clk **pcc3_uart_clks[ARRAY_SIZE(pcc3_uart_clk_ids) + 1] __initdata;
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static void __init imx7ulp_clk_scg1_init(struct device_node *np)
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{
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struct clk_hw_onecell_data *clk_data;
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@ -135,6 +148,7 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
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struct clk_hw_onecell_data *clk_data;
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struct clk_hw **clks;
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void __iomem *base;
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int i;
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clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC2_END),
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GFP_KERNEL);
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@ -173,6 +187,14 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
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imx_check_clk_hws(clks, clk_data->num);
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
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for (i = 0; i < ARRAY_SIZE(pcc2_uart_clk_ids); i++) {
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int index = pcc2_uart_clk_ids[i];
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pcc2_uart_clks[i] = &clks[index]->clk;
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}
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imx_register_uart_clocks(pcc2_uart_clks);
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}
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CLK_OF_DECLARE(imx7ulp_clk_pcc2, "fsl,imx7ulp-pcc2", imx7ulp_clk_pcc2_init);
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@ -181,6 +203,7 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
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struct clk_hw_onecell_data *clk_data;
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struct clk_hw **clks;
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void __iomem *base;
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int i;
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clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC3_END),
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GFP_KERNEL);
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@ -218,6 +241,14 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
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imx_check_clk_hws(clks, clk_data->num);
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
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for (i = 0; i < ARRAY_SIZE(pcc3_uart_clk_ids); i++) {
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int index = pcc3_uart_clk_ids[i];
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pcc3_uart_clks[i] = &clks[index]->clk;
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}
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imx_register_uart_clocks(pcc3_uart_clks);
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}
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CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init);
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@ -22,27 +22,10 @@ static u32 share_count_sai3;
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static u32 share_count_sai4;
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static u32 share_count_sai5;
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static u32 share_count_sai6;
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static u32 share_count_dcss;
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static u32 share_count_disp;
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static u32 share_count_pdm;
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static u32 share_count_nand;
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#define PLL_1416X_RATE(_rate, _m, _p, _s) \
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{ \
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.rate = (_rate), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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}
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#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
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{ \
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.rate = (_rate), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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.kdiv = (_k), \
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}
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static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
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PLL_1416X_RATE(1800000000U, 225, 3, 0),
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PLL_1416X_RATE(1600000000U, 200, 3, 0),
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@ -55,8 +38,8 @@ static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
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};
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static const struct imx_pll14xx_rate_table imx8mm_audiopll_tbl[] = {
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PLL_1443X_RATE(786432000U, 655, 5, 2, 23593),
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PLL_1443X_RATE(722534400U, 301, 5, 1, 3670),
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PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
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PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
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};
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static const struct imx_pll14xx_rate_table imx8mm_videopll_tbl[] = {
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@ -68,43 +51,43 @@ static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
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PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
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};
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static struct imx_pll14xx_clk imx8mm_audio_pll __initdata = {
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static struct imx_pll14xx_clk imx8mm_audio_pll = {
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.type = PLL_1443X,
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.rate_table = imx8mm_audiopll_tbl,
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.rate_count = ARRAY_SIZE(imx8mm_audiopll_tbl),
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};
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static struct imx_pll14xx_clk imx8mm_video_pll __initdata = {
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static struct imx_pll14xx_clk imx8mm_video_pll = {
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.type = PLL_1443X,
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.rate_table = imx8mm_videopll_tbl,
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.rate_count = ARRAY_SIZE(imx8mm_videopll_tbl),
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};
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static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
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static struct imx_pll14xx_clk imx8mm_dram_pll = {
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.type = PLL_1443X,
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.rate_table = imx8mm_drampll_tbl,
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.rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
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};
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static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
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static struct imx_pll14xx_clk imx8mm_arm_pll = {
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.type = PLL_1416X,
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.rate_table = imx8mm_pll1416x_tbl,
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.rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
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};
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static struct imx_pll14xx_clk imx8mm_gpu_pll __initdata = {
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static struct imx_pll14xx_clk imx8mm_gpu_pll = {
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.type = PLL_1416X,
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.rate_table = imx8mm_pll1416x_tbl,
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.rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
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};
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static struct imx_pll14xx_clk imx8mm_vpu_pll __initdata = {
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static struct imx_pll14xx_clk imx8mm_vpu_pll = {
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.type = PLL_1416X,
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.rate_table = imx8mm_pll1416x_tbl,
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.rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
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};
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static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
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static struct imx_pll14xx_clk imx8mm_sys_pll = {
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.type = PLL_1416X,
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.rate_table = imx8mm_pll1416x_tbl,
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.rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
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@ -192,10 +175,10 @@ static const char *imx8mm_vpu_g1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_8
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static const char *imx8mm_vpu_g2_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", "sys_pll2_1000m",
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"sys_pll1_100m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", };
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static const char *imx8mm_disp_dtrc_sels[] = {"osc_24m", "video_pll2_out", "sys_pll1_800m", "sys_pll2_1000m",
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static const char *imx8mm_disp_dtrc_sels[] = {"osc_24m", "dummy", "sys_pll1_800m", "sys_pll2_1000m",
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"sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out", };
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static const char *imx8mm_disp_dc8000_sels[] = {"osc_24m", "video_pll2_out", "sys_pll1_800m", "sys_pll2_1000m",
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static const char *imx8mm_disp_dc8000_sels[] = {"osc_24m", "dummy", "sys_pll1_800m", "sys_pll2_1000m",
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"sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out", };
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static const char *imx8mm_pcie1_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m",
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@ -249,7 +232,7 @@ static const char *imx8mm_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll
|
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static const char *imx8mm_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", "sys_pll1_400m",
|
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"audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll1_out", };
|
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|
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static const char *imx8mm_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
|
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static const char *imx8mm_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
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"audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
|
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static const char *imx8mm_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
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@ -304,13 +287,13 @@ static const char *imx8mm_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_1
|
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"sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
|
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|
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static const char *imx8mm_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
|
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"sys3_pll2_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
|
||||
"sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
|
||||
|
||||
static const char *imx8mm_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
|
||||
"sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
|
||||
|
||||
static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", "sys_pll1_40m",
|
||||
"video_pll1_out", "sys_pll1_800m", "audio_pll1_out", "clk_ext1" };
|
||||
"video_pll1_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" };
|
||||
|
||||
static const char *imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
|
||||
"sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
|
||||
@ -364,7 +347,7 @@ static const char *imx8mm_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_
|
||||
"sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char *imx8mm_vpu_h1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", "sys_pll2_1000m",
|
||||
"audio_pll2_out", "sys_pll2_125m", "sys_pll3_clk", "audio_pll1_out", };
|
||||
"audio_pll2_out", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", };
|
||||
|
||||
static const char *imx8mm_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
|
||||
|
||||
@ -374,7 +357,7 @@ static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m",
|
||||
static struct clk *clks[IMX8MM_CLK_END];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static struct clk ** const uart_clks[] __initconst = {
|
||||
static struct clk ** const uart_clks[] = {
|
||||
&clks[IMX8MM_CLK_UART1_ROOT],
|
||||
&clks[IMX8MM_CLK_UART2_ROOT],
|
||||
&clks[IMX8MM_CLK_UART3_ROOT],
|
||||
@ -382,19 +365,20 @@ static struct clk ** const uart_clks[] __initconst = {
|
||||
NULL
|
||||
};
|
||||
|
||||
static int __init imx8mm_clocks_init(struct device_node *ccm_node)
|
||||
static int imx8mm_clocks_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
void __iomem *base;
|
||||
int ret;
|
||||
|
||||
clks[IMX8MM_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
|
||||
clks[IMX8MM_CLK_24M] = of_clk_get_by_name(ccm_node, "osc_24m");
|
||||
clks[IMX8MM_CLK_32K] = of_clk_get_by_name(ccm_node, "osc_32k");
|
||||
clks[IMX8MM_CLK_EXT1] = of_clk_get_by_name(ccm_node, "clk_ext1");
|
||||
clks[IMX8MM_CLK_EXT2] = of_clk_get_by_name(ccm_node, "clk_ext2");
|
||||
clks[IMX8MM_CLK_EXT3] = of_clk_get_by_name(ccm_node, "clk_ext3");
|
||||
clks[IMX8MM_CLK_EXT4] = of_clk_get_by_name(ccm_node, "clk_ext4");
|
||||
clks[IMX8MM_CLK_24M] = of_clk_get_by_name(np, "osc_24m");
|
||||
clks[IMX8MM_CLK_32K] = of_clk_get_by_name(np, "osc_32k");
|
||||
clks[IMX8MM_CLK_EXT1] = of_clk_get_by_name(np, "clk_ext1");
|
||||
clks[IMX8MM_CLK_EXT2] = of_clk_get_by_name(np, "clk_ext2");
|
||||
clks[IMX8MM_CLK_EXT3] = of_clk_get_by_name(np, "clk_ext3");
|
||||
clks[IMX8MM_CLK_EXT4] = of_clk_get_by_name(np, "clk_ext4");
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
@ -480,10 +464,10 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node)
|
||||
clks[IMX8MM_SYS_PLL2_500M] = imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
|
||||
clks[IMX8MM_SYS_PLL2_1000M] = imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
|
||||
|
||||
np = ccm_node;
|
||||
base = of_iomap(np, 0);
|
||||
if (WARN_ON(!base))
|
||||
return -ENOMEM;
|
||||
np = dev->of_node;
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (WARN_ON(IS_ERR(base)))
|
||||
return PTR_ERR(base);
|
||||
|
||||
/* Core Slice */
|
||||
clks[IMX8MM_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels));
|
||||
@ -631,7 +615,7 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node)
|
||||
clks[IMX8MM_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
|
||||
clks[IMX8MM_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
|
||||
clks[IMX8MM_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
|
||||
clks[IMX8MM_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0);
|
||||
clks[IMX8MM_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0);
|
||||
clks[IMX8MM_CLK_GPU3D_ROOT] = imx_clk_gate4("gpu3d_root_clk", "gpu3d_div", base + 0x44f0, 0);
|
||||
clks[IMX8MM_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
|
||||
clks[IMX8MM_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
|
||||
@ -644,10 +628,10 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node)
|
||||
clks[IMX8MM_CLK_VPU_G2_ROOT] = imx_clk_gate4("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0);
|
||||
clks[IMX8MM_CLK_PDM_ROOT] = imx_clk_gate2_shared2("pdm_root_clk", "pdm", base + 0x45b0, 0, &share_count_pdm);
|
||||
clks[IMX8MM_CLK_PDM_IPG] = imx_clk_gate2_shared2("pdm_ipg_clk", "ipg_audio_root", base + 0x45b0, 0, &share_count_pdm);
|
||||
clks[IMX8MM_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk", "disp_dc8000", base + 0x45d0, 0, &share_count_dcss);
|
||||
clks[IMX8MM_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_dcss);
|
||||
clks[IMX8MM_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_dcss);
|
||||
clks[IMX8MM_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_dcss);
|
||||
clks[IMX8MM_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk", "disp_dc8000", base + 0x45d0, 0, &share_count_disp);
|
||||
clks[IMX8MM_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_disp);
|
||||
clks[IMX8MM_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_disp);
|
||||
clks[IMX8MM_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_disp);
|
||||
clks[IMX8MM_CLK_USDHC3_ROOT] = imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0);
|
||||
clks[IMX8MM_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0);
|
||||
clks[IMX8MM_CLK_VPU_DEC_ROOT] = imx_clk_gate4("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0);
|
||||
@ -675,11 +659,30 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node)
|
||||
ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
if (ret < 0) {
|
||||
pr_err("failed to register clks for i.MX8MM\n");
|
||||
return -EINVAL;
|
||||
goto unregister_clks;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
|
||||
return 0;
|
||||
|
||||
unregister_clks:
|
||||
imx_unregister_clocks(clks, ARRAY_SIZE(clks));
|
||||
|
||||
return ret;
|
||||
}
|
||||
CLK_OF_DECLARE_DRIVER(imx8mm, "fsl,imx8mm-ccm", imx8mm_clocks_init);
|
||||
|
||||
static const struct of_device_id imx8mm_clk_of_match[] = {
|
||||
{ .compatible = "fsl,imx8mm-ccm" },
|
||||
{ /* Sentinel */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, imx8mm_clk_of_match);
|
||||
|
||||
static struct platform_driver imx8mm_clk_driver = {
|
||||
.probe = imx8mm_clocks_probe,
|
||||
.driver = {
|
||||
.name = "imx8mm-ccm",
|
||||
.of_match_table = of_match_ptr(imx8mm_clk_of_match),
|
||||
},
|
||||
};
|
||||
module_platform_driver(imx8mm_clk_driver);
|
||||
|
||||
660
drivers/clk/imx/clk-imx8mn.c
Normal file
660
drivers/clk/imx/clk-imx8mn.c
Normal file
@ -0,0 +1,660 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2018-2019 NXP.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx8mn-clock.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
static u32 share_count_sai2;
|
||||
static u32 share_count_sai3;
|
||||
static u32 share_count_sai5;
|
||||
static u32 share_count_sai6;
|
||||
static u32 share_count_sai7;
|
||||
static u32 share_count_disp;
|
||||
static u32 share_count_pdm;
|
||||
static u32 share_count_nand;
|
||||
|
||||
enum {
|
||||
ARM_PLL,
|
||||
GPU_PLL,
|
||||
VPU_PLL,
|
||||
SYS_PLL1,
|
||||
SYS_PLL2,
|
||||
SYS_PLL3,
|
||||
DRAM_PLL,
|
||||
AUDIO_PLL1,
|
||||
AUDIO_PLL2,
|
||||
VIDEO_PLL2,
|
||||
NR_PLLS,
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
|
||||
PLL_1416X_RATE(1800000000U, 225, 3, 0),
|
||||
PLL_1416X_RATE(1600000000U, 200, 3, 0),
|
||||
PLL_1416X_RATE(1500000000U, 375, 3, 1),
|
||||
PLL_1416X_RATE(1400000000U, 350, 3, 1),
|
||||
PLL_1416X_RATE(1200000000U, 300, 3, 1),
|
||||
PLL_1416X_RATE(1000000000U, 250, 3, 1),
|
||||
PLL_1416X_RATE(800000000U, 200, 3, 1),
|
||||
PLL_1416X_RATE(750000000U, 250, 2, 2),
|
||||
PLL_1416X_RATE(700000000U, 350, 3, 2),
|
||||
PLL_1416X_RATE(600000000U, 300, 3, 2),
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mn_audiopll_tbl[] = {
|
||||
PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
|
||||
PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mn_videopll_tbl[] = {
|
||||
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
|
||||
PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
|
||||
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_audio_pll = {
|
||||
.type = PLL_1443X,
|
||||
.rate_table = imx8mn_audiopll_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_audiopll_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_video_pll = {
|
||||
.type = PLL_1443X,
|
||||
.rate_table = imx8mn_videopll_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_videopll_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_dram_pll = {
|
||||
.type = PLL_1443X,
|
||||
.rate_table = imx8mn_drampll_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_drampll_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_arm_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mn_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_gpu_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mn_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_vpu_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mn_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_sys_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mn_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
|
||||
};
|
||||
|
||||
static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
|
||||
static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
|
||||
static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
|
||||
static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
|
||||
static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
|
||||
static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
|
||||
static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
|
||||
static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
|
||||
static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
|
||||
static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
|
||||
static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
|
||||
|
||||
static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
|
||||
"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
|
||||
"audio_pll1_out", "sys_pll3_out", };
|
||||
|
||||
static const char * const imx8mn_gpu_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
|
||||
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_gpu_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
|
||||
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m",
|
||||
"sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "sys_pll1_100m",};
|
||||
|
||||
static const char * const imx8mn_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
|
||||
"sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
|
||||
"video_pll1_out", "sys_pll3_out", };
|
||||
|
||||
static const char * const imx8mn_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
|
||||
"sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
|
||||
"sys_pll2_250m", "audio_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_disp_axi_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m",
|
||||
"sys_pll3_out", "sys_pll1_40m", "audio_pll2_out",
|
||||
"clk_ext1", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_disp_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll1_800m",
|
||||
"sys_pll3_out", "sys_pll1_40m", "audio_pll2_out",
|
||||
"clk_ext1", "clk_ext3", };
|
||||
|
||||
static const char * const imx8mn_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
|
||||
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
|
||||
"clk_ext4", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
|
||||
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
|
||||
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
|
||||
"sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
|
||||
"sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
|
||||
"audio_pll1_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
|
||||
"sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out",
|
||||
"audio_pll1_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m",
|
||||
"sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"audio_pll1_out", "sys_pll1_266m", };
|
||||
|
||||
static const char * const imx8mn_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
|
||||
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
|
||||
"sys_pll2_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out",
|
||||
"audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m",
|
||||
"sys_pll3_out", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext2", "clk_ext3", };
|
||||
|
||||
static const char * const imx8mn_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext2", "clk_ext3", };
|
||||
|
||||
static const char * const imx8mn_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
|
||||
"sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
|
||||
"video_pll1_out", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
|
||||
"clk_ext1", "clk_ext2", "clk_ext3",
|
||||
"clk_ext4", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
|
||||
"sys_pll2_200m", "sys_pll2_500m", "video_pll1_out",
|
||||
"audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
|
||||
"sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
|
||||
"sys_pll2_250m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
|
||||
"sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
|
||||
"sys_pll3_out", "sys_pll1_100m", };
|
||||
|
||||
static const char * const imx8mn_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
|
||||
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
|
||||
"audio_pll2_out", "sys_pll1_100m", };
|
||||
|
||||
static const char * const imx8mn_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
|
||||
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
|
||||
"audio_pll2_out", "sys_pll1_100m", };
|
||||
|
||||
static const char * const imx8mn_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
|
||||
"audio_pll2_out", "sys_pll1_133m", };
|
||||
|
||||
static const char * const imx8mn_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
|
||||
"audio_pll2_out", "sys_pll1_133m", };
|
||||
|
||||
static const char * const imx8mn_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
|
||||
"audio_pll2_out", "sys_pll1_133m", };
|
||||
|
||||
static const char * const imx8mn_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
|
||||
"audio_pll2_out", "sys_pll1_133m", };
|
||||
|
||||
static const char * const imx8mn_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
|
||||
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
|
||||
"clk_ext4", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
|
||||
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
|
||||
"clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
|
||||
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
|
||||
"clk_ext4", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
|
||||
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
|
||||
"clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
|
||||
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
|
||||
"clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
|
||||
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
|
||||
"clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_gic_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
|
||||
"sys_pll2_100m", "sys_pll1_800m", "clk_ext2",
|
||||
"clk_ext4", "audio_pll2_out" };
|
||||
|
||||
static const char * const imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
|
||||
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
|
||||
"sys_pll2_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
|
||||
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
|
||||
"sys_pll2_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
|
||||
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
|
||||
"sys_pll1_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
|
||||
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
|
||||
"sys_pll1_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
|
||||
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
|
||||
"sys_pll1_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
|
||||
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
|
||||
"sys_pll1_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
|
||||
"vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
|
||||
"sys_pll1_80m", "sys_pll2_166m", };
|
||||
|
||||
static const char * const imx8mn_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_out",
|
||||
"sys_pll3_out", "sys_pll2_200m", "sys_pll1_266m",
|
||||
"sys_pll2_500m", "sys_pll1_100m", };
|
||||
|
||||
static const char * const imx8mn_dsi_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_dsi_phy_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_100m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_dsi_dbi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_100m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
|
||||
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
|
||||
"audio_pll2_out", "sys_pll1_100m", };
|
||||
|
||||
static const char * const imx8mn_camera_pixel_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_csi1_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_csi2_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
|
||||
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
|
||||
"sys_pll2_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
|
||||
|
||||
static const char * const imx8mn_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m",
|
||||
"sys_pll1_200m", "audio_pll2_out", "vpu_pll",
|
||||
"sys_pll1_80m", };
|
||||
static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m",
|
||||
"sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
|
||||
"video_pll1_out", "osc_32k", };
|
||||
|
||||
static struct clk *clks[IMX8MN_CLK_END];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static struct clk ** const uart_clks[] = {
|
||||
&clks[IMX8MN_CLK_UART1_ROOT],
|
||||
&clks[IMX8MN_CLK_UART2_ROOT],
|
||||
&clks[IMX8MN_CLK_UART3_ROOT],
|
||||
&clks[IMX8MN_CLK_UART4_ROOT],
|
||||
NULL
|
||||
};
|
||||
|
||||
static int imx8mn_clocks_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
void __iomem *base;
|
||||
int ret;
|
||||
|
||||
clks[IMX8MN_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
|
||||
clks[IMX8MN_CLK_24M] = of_clk_get_by_name(np, "osc_24m");
|
||||
clks[IMX8MN_CLK_32K] = of_clk_get_by_name(np, "osc_32k");
|
||||
clks[IMX8MN_CLK_EXT1] = of_clk_get_by_name(np, "clk_ext1");
|
||||
clks[IMX8MN_CLK_EXT2] = of_clk_get_by_name(np, "clk_ext2");
|
||||
clks[IMX8MN_CLK_EXT3] = of_clk_get_by_name(np, "clk_ext3");
|
||||
clks[IMX8MN_CLK_EXT4] = of_clk_get_by_name(np, "clk_ext4");
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
if (WARN_ON(!base)) {
|
||||
ret = -ENOMEM;
|
||||
goto unregister_clks;
|
||||
}
|
||||
|
||||
clks[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_SYS_PLL1_REF_SEL] = imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_SYS_PLL2_REF_SEL] = imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
|
||||
clks[IMX8MN_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx8mn_audio_pll);
|
||||
clks[IMX8MN_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx8mn_audio_pll);
|
||||
clks[IMX8MN_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx8mn_video_pll);
|
||||
clks[IMX8MN_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx8mn_dram_pll);
|
||||
clks[IMX8MN_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx8mn_gpu_pll);
|
||||
clks[IMX8MN_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx8mn_vpu_pll);
|
||||
clks[IMX8MN_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mn_arm_pll);
|
||||
clks[IMX8MN_SYS_PLL1] = imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mn_sys_pll);
|
||||
clks[IMX8MN_SYS_PLL2] = imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mn_sys_pll);
|
||||
clks[IMX8MN_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mn_sys_pll);
|
||||
|
||||
/* PLL bypass out */
|
||||
clks[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_mux_flags("audio_pll1_bypass", base, 4, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_mux_flags("audio_pll2_bypass", base + 0x14, 4, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_VIDEO_PLL1_BYPASS] = imx_clk_mux_flags("video_pll1_bypass", base + 0x28, 4, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", base + 0x64, 4, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", base + 0x74, 4, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
|
||||
/* unbypass all the plls */
|
||||
clk_set_parent(clks[IMX8MN_AUDIO_PLL1_BYPASS], clks[IMX8MN_AUDIO_PLL1]);
|
||||
clk_set_parent(clks[IMX8MN_AUDIO_PLL2_BYPASS], clks[IMX8MN_AUDIO_PLL2]);
|
||||
clk_set_parent(clks[IMX8MN_VIDEO_PLL1_BYPASS], clks[IMX8MN_VIDEO_PLL1]);
|
||||
clk_set_parent(clks[IMX8MN_DRAM_PLL_BYPASS], clks[IMX8MN_DRAM_PLL]);
|
||||
clk_set_parent(clks[IMX8MN_GPU_PLL_BYPASS], clks[IMX8MN_GPU_PLL]);
|
||||
clk_set_parent(clks[IMX8MN_VPU_PLL_BYPASS], clks[IMX8MN_VPU_PLL]);
|
||||
clk_set_parent(clks[IMX8MN_ARM_PLL_BYPASS], clks[IMX8MN_ARM_PLL]);
|
||||
clk_set_parent(clks[IMX8MN_SYS_PLL1_BYPASS], clks[IMX8MN_SYS_PLL1]);
|
||||
clk_set_parent(clks[IMX8MN_SYS_PLL2_BYPASS], clks[IMX8MN_SYS_PLL2]);
|
||||
clk_set_parent(clks[IMX8MN_SYS_PLL3_BYPASS], clks[IMX8MN_SYS_PLL3]);
|
||||
|
||||
/* PLL out gate */
|
||||
clks[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base, 13);
|
||||
clks[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13);
|
||||
clks[IMX8MN_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13);
|
||||
clks[IMX8MN_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13);
|
||||
clks[IMX8MN_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11);
|
||||
clks[IMX8MN_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11);
|
||||
clks[IMX8MN_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11);
|
||||
clks[IMX8MN_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11);
|
||||
clks[IMX8MN_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11);
|
||||
clks[IMX8MN_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11);
|
||||
|
||||
/* SYS PLL fixed output */
|
||||
clks[IMX8MN_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
|
||||
clks[IMX8MN_SYS_PLL1_80M] = imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
|
||||
clks[IMX8MN_SYS_PLL1_100M] = imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
|
||||
clks[IMX8MN_SYS_PLL1_133M] = imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
|
||||
clks[IMX8MN_SYS_PLL1_160M] = imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
|
||||
clks[IMX8MN_SYS_PLL1_200M] = imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
|
||||
clks[IMX8MN_SYS_PLL1_266M] = imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
|
||||
clks[IMX8MN_SYS_PLL1_400M] = imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
|
||||
clks[IMX8MN_SYS_PLL1_800M] = imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
|
||||
|
||||
clks[IMX8MN_SYS_PLL2_50M] = imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
|
||||
clks[IMX8MN_SYS_PLL2_100M] = imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
|
||||
clks[IMX8MN_SYS_PLL2_125M] = imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
|
||||
clks[IMX8MN_SYS_PLL2_166M] = imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
|
||||
clks[IMX8MN_SYS_PLL2_200M] = imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
|
||||
clks[IMX8MN_SYS_PLL2_250M] = imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
|
||||
clks[IMX8MN_SYS_PLL2_333M] = imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
|
||||
clks[IMX8MN_SYS_PLL2_500M] = imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
|
||||
clks[IMX8MN_SYS_PLL2_1000M] = imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
|
||||
|
||||
np = dev->of_node;
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (WARN_ON(IS_ERR(base))) {
|
||||
ret = PTR_ERR(base);
|
||||
goto unregister_clks;
|
||||
}
|
||||
|
||||
/* CORE */
|
||||
clks[IMX8MN_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels));
|
||||
clks[IMX8MN_CLK_GPU_CORE_SRC] = imx_clk_mux2("gpu_core_src", base + 0x8180, 24, 3, imx8mn_gpu_core_sels, ARRAY_SIZE(imx8mn_gpu_core_sels));
|
||||
clks[IMX8MN_CLK_GPU_SHADER_SRC] = imx_clk_mux2("gpu_shader_src", base + 0x8200, 24, 3, imx8mn_gpu_shader_sels, ARRAY_SIZE(imx8mn_gpu_shader_sels));
|
||||
clks[IMX8MN_CLK_A53_CG] = imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28);
|
||||
clks[IMX8MN_CLK_GPU_CORE_CG] = imx_clk_gate3("gpu_core_cg", "gpu_core_src", base + 0x8180, 28);
|
||||
clks[IMX8MN_CLK_GPU_SHADER_CG] = imx_clk_gate3("gpu_shader_cg", "gpu_shader_src", base + 0x8200, 28);
|
||||
|
||||
clks[IMX8MN_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
|
||||
clks[IMX8MN_CLK_GPU_CORE_DIV] = imx_clk_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3);
|
||||
clks[IMX8MN_CLK_GPU_SHADER_DIV] = imx_clk_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0, 3);
|
||||
|
||||
/* BUS */
|
||||
clks[IMX8MN_CLK_MAIN_AXI] = imx8m_clk_composite_critical("main_axi", imx8mn_main_axi_sels, base + 0x8800);
|
||||
clks[IMX8MN_CLK_ENET_AXI] = imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels, base + 0x8880);
|
||||
clks[IMX8MN_CLK_NAND_USDHC_BUS] = imx8m_clk_composite("nand_usdhc_bus", imx8mn_nand_usdhc_sels, base + 0x8900);
|
||||
clks[IMX8MN_CLK_DISP_AXI] = imx8m_clk_composite("disp_axi", imx8mn_disp_axi_sels, base + 0x8a00);
|
||||
clks[IMX8MN_CLK_DISP_APB] = imx8m_clk_composite("disp_apb", imx8mn_disp_apb_sels, base + 0x8a80);
|
||||
clks[IMX8MN_CLK_USB_BUS] = imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80);
|
||||
clks[IMX8MN_CLK_GPU_AXI] = imx8m_clk_composite("gpu_axi", imx8mn_gpu_axi_sels, base + 0x8c00);
|
||||
clks[IMX8MN_CLK_GPU_AHB] = imx8m_clk_composite("gpu_ahb", imx8mn_gpu_ahb_sels, base + 0x8c80);
|
||||
clks[IMX8MN_CLK_NOC] = imx8m_clk_composite_critical("noc", imx8mn_noc_sels, base + 0x8d00);
|
||||
|
||||
clks[IMX8MN_CLK_AHB] = imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels, base + 0x9000);
|
||||
clks[IMX8MN_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mn_audio_ahb_sels, base + 0x9100);
|
||||
clks[IMX8MN_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1);
|
||||
clks[IMX8MN_CLK_IPG_AUDIO_ROOT] = imx_clk_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1);
|
||||
clks[IMX8MN_CLK_DRAM_CORE] = imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mn_dram_core_sels, ARRAY_SIZE(imx8mn_dram_core_sels), CLK_IS_CRITICAL);
|
||||
clks[IMX8MN_CLK_DRAM_ALT] = imx8m_clk_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000);
|
||||
clks[IMX8MN_CLK_DRAM_APB] = imx8m_clk_composite_critical("dram_apb", imx8mn_dram_apb_sels, base + 0xa080);
|
||||
clks[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500);
|
||||
clks[IMX8MN_CLK_SAI2] = imx8m_clk_composite("sai2", imx8mn_sai2_sels, base + 0xa600);
|
||||
clks[IMX8MN_CLK_SAI3] = imx8m_clk_composite("sai3", imx8mn_sai3_sels, base + 0xa680);
|
||||
clks[IMX8MN_CLK_SAI5] = imx8m_clk_composite("sai5", imx8mn_sai5_sels, base + 0xa780);
|
||||
clks[IMX8MN_CLK_SAI6] = imx8m_clk_composite("sai6", imx8mn_sai6_sels, base + 0xa800);
|
||||
clks[IMX8MN_CLK_SPDIF1] = imx8m_clk_composite("spdif1", imx8mn_spdif1_sels, base + 0xa880);
|
||||
clks[IMX8MN_CLK_ENET_REF] = imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels, base + 0xa980);
|
||||
clks[IMX8MN_CLK_ENET_TIMER] = imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels, base + 0xaa00);
|
||||
clks[IMX8MN_CLK_ENET_PHY_REF] = imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels, base + 0xaa80);
|
||||
clks[IMX8MN_CLK_NAND] = imx8m_clk_composite("nand", imx8mn_nand_sels, base + 0xab00);
|
||||
clks[IMX8MN_CLK_QSPI] = imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80);
|
||||
clks[IMX8MN_CLK_USDHC1] = imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels, base + 0xac00);
|
||||
clks[IMX8MN_CLK_USDHC2] = imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels, base + 0xac80);
|
||||
clks[IMX8MN_CLK_I2C1] = imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00);
|
||||
clks[IMX8MN_CLK_I2C2] = imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80);
|
||||
clks[IMX8MN_CLK_I2C3] = imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00);
|
||||
clks[IMX8MN_CLK_I2C4] = imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80);
|
||||
clks[IMX8MN_CLK_UART1] = imx8m_clk_composite("uart1", imx8mn_uart1_sels, base + 0xaf00);
|
||||
clks[IMX8MN_CLK_UART2] = imx8m_clk_composite("uart2", imx8mn_uart2_sels, base + 0xaf80);
|
||||
clks[IMX8MN_CLK_UART3] = imx8m_clk_composite("uart3", imx8mn_uart3_sels, base + 0xb000);
|
||||
clks[IMX8MN_CLK_UART4] = imx8m_clk_composite("uart4", imx8mn_uart4_sels, base + 0xb080);
|
||||
clks[IMX8MN_CLK_USB_CORE_REF] = imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100);
|
||||
clks[IMX8MN_CLK_USB_PHY_REF] = imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180);
|
||||
clks[IMX8MN_CLK_GIC] = imx8m_clk_composite_critical("gic", imx8mn_gic_sels, base + 0xb200);
|
||||
clks[IMX8MN_CLK_ECSPI1] = imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280);
|
||||
clks[IMX8MN_CLK_ECSPI2] = imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300);
|
||||
clks[IMX8MN_CLK_PWM1] = imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380);
|
||||
clks[IMX8MN_CLK_PWM2] = imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400);
|
||||
clks[IMX8MN_CLK_PWM3] = imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480);
|
||||
clks[IMX8MN_CLK_PWM4] = imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500);
|
||||
clks[IMX8MN_CLK_WDOG] = imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900);
|
||||
clks[IMX8MN_CLK_WRCLK] = imx8m_clk_composite("wrclk", imx8mn_wrclk_sels, base + 0xb980);
|
||||
clks[IMX8MN_CLK_CLKO1] = imx8m_clk_composite("clko1", imx8mn_clko1_sels, base + 0xba00);
|
||||
clks[IMX8MN_CLK_CLKO2] = imx8m_clk_composite("clko2", imx8mn_clko2_sels, base + 0xba80);
|
||||
clks[IMX8MN_CLK_DSI_CORE] = imx8m_clk_composite("dsi_core", imx8mn_dsi_core_sels, base + 0xbb00);
|
||||
clks[IMX8MN_CLK_DSI_PHY_REF] = imx8m_clk_composite("dsi_phy_ref", imx8mn_dsi_phy_sels, base + 0xbb80);
|
||||
clks[IMX8MN_CLK_DSI_DBI] = imx8m_clk_composite("dsi_dbi", imx8mn_dsi_dbi_sels, base + 0xbc00);
|
||||
clks[IMX8MN_CLK_USDHC3] = imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels, base + 0xbc80);
|
||||
clks[IMX8MN_CLK_CAMERA_PIXEL] = imx8m_clk_composite("camera_pixel", imx8mn_camera_pixel_sels, base + 0xbd00);
|
||||
clks[IMX8MN_CLK_CSI1_PHY_REF] = imx8m_clk_composite("csi1_phy_ref", imx8mn_csi1_phy_sels, base + 0xbd80);
|
||||
clks[IMX8MN_CLK_CSI2_PHY_REF] = imx8m_clk_composite("csi2_phy_ref", imx8mn_csi2_phy_sels, base + 0xbf00);
|
||||
clks[IMX8MN_CLK_CSI2_ESC] = imx8m_clk_composite("csi2_esc", imx8mn_csi2_esc_sels, base + 0xbf80);
|
||||
clks[IMX8MN_CLK_ECSPI3] = imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180);
|
||||
clks[IMX8MN_CLK_PDM] = imx8m_clk_composite("pdm", imx8mn_pdm_sels, base + 0xc200);
|
||||
clks[IMX8MN_CLK_SAI7] = imx8m_clk_composite("sai7", imx8mn_sai7_sels, base + 0xc300);
|
||||
|
||||
clks[IMX8MN_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0);
|
||||
clks[IMX8MN_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0);
|
||||
clks[IMX8MN_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0);
|
||||
clks[IMX8MN_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0);
|
||||
clks[IMX8MN_CLK_GPIO1_ROOT] = imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0);
|
||||
clks[IMX8MN_CLK_GPIO2_ROOT] = imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0);
|
||||
clks[IMX8MN_CLK_GPIO3_ROOT] = imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0);
|
||||
clks[IMX8MN_CLK_GPIO4_ROOT] = imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0);
|
||||
clks[IMX8MN_CLK_GPIO5_ROOT] = imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0);
|
||||
clks[IMX8MN_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0);
|
||||
clks[IMX8MN_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0);
|
||||
clks[IMX8MN_CLK_I2C3_ROOT] = imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0);
|
||||
clks[IMX8MN_CLK_I2C4_ROOT] = imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0);
|
||||
clks[IMX8MN_CLK_MU_ROOT] = imx_clk_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0);
|
||||
clks[IMX8MN_CLK_OCOTP_ROOT] = imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0);
|
||||
clks[IMX8MN_CLK_PWM1_ROOT] = imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0);
|
||||
clks[IMX8MN_CLK_PWM2_ROOT] = imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0);
|
||||
clks[IMX8MN_CLK_PWM3_ROOT] = imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0);
|
||||
clks[IMX8MN_CLK_PWM4_ROOT] = imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0);
|
||||
clks[IMX8MN_CLK_QSPI_ROOT] = imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0);
|
||||
clks[IMX8MN_CLK_NAND_ROOT] = imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand);
|
||||
clks[IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand);
|
||||
clks[IMX8MN_CLK_SAI2_ROOT] = imx_clk_gate2_shared2("sai2_root_clk", "sai2", base + 0x4340, 0, &share_count_sai2);
|
||||
clks[IMX8MN_CLK_SAI2_IPG] = imx_clk_gate2_shared2("sai2_ipg_clk", "ipg_audio_root", base + 0x4340, 0, &share_count_sai2);
|
||||
clks[IMX8MN_CLK_SAI3_ROOT] = imx_clk_gate2_shared2("sai3_root_clk", "sai3", base + 0x4350, 0, &share_count_sai3);
|
||||
clks[IMX8MN_CLK_SAI3_IPG] = imx_clk_gate2_shared2("sai3_ipg_clk", "ipg_audio_root", base + 0x4350, 0, &share_count_sai3);
|
||||
clks[IMX8MN_CLK_SAI5_ROOT] = imx_clk_gate2_shared2("sai5_root_clk", "sai5", base + 0x4370, 0, &share_count_sai5);
|
||||
clks[IMX8MN_CLK_SAI5_IPG] = imx_clk_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
|
||||
clks[IMX8MN_CLK_SAI6_ROOT] = imx_clk_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
|
||||
clks[IMX8MN_CLK_SAI6_IPG] = imx_clk_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
|
||||
clks[IMX8MN_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
|
||||
clks[IMX8MN_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
|
||||
clks[IMX8MN_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
|
||||
clks[IMX8MN_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
|
||||
clks[IMX8MN_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0);
|
||||
clks[IMX8MN_CLK_GPU_CORE_ROOT] = imx_clk_gate4("gpu_core_root_clk", "gpu_core_div", base + 0x44f0, 0);
|
||||
clks[IMX8MN_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
|
||||
clks[IMX8MN_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
|
||||
clks[IMX8MN_CLK_WDOG1_ROOT] = imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0);
|
||||
clks[IMX8MN_CLK_WDOG2_ROOT] = imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0);
|
||||
clks[IMX8MN_CLK_WDOG3_ROOT] = imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0);
|
||||
clks[IMX8MN_CLK_GPU_BUS_ROOT] = imx_clk_gate4("gpu_root_clk", "gpu_axi", base + 0x4570, 0);
|
||||
clks[IMX8MN_CLK_ASRC_ROOT] = imx_clk_gate4("asrc_root_clk", "audio_ahb", base + 0x4580, 0);
|
||||
clks[IMX8MN_CLK_PDM_ROOT] = imx_clk_gate2_shared2("pdm_root_clk", "pdm", base + 0x45b0, 0, &share_count_pdm);
|
||||
clks[IMX8MN_CLK_PDM_IPG] = imx_clk_gate2_shared2("pdm_ipg_clk", "ipg_audio_root", base + 0x45b0, 0, &share_count_pdm);
|
||||
clks[IMX8MN_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_disp);
|
||||
clks[IMX8MN_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_disp);
|
||||
clks[IMX8MN_CLK_CAMERA_PIXEL_ROOT] = imx_clk_gate2_shared2("camera_pixel_clk", "camera_pixel", base + 0x45d0, 0, &share_count_disp);
|
||||
clks[IMX8MN_CLK_DISP_PIXEL_ROOT] = imx_clk_gate2_shared2("disp_pixel_clk", "disp_pixel", base + 0x45d0, 0, &share_count_disp);
|
||||
clks[IMX8MN_CLK_USDHC3_ROOT] = imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0);
|
||||
clks[IMX8MN_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0);
|
||||
clks[IMX8MN_CLK_SDMA1_ROOT] = imx_clk_gate4("sdma1_clk", "ipg_root", base + 0x43a0, 0);
|
||||
clks[IMX8MN_CLK_SDMA2_ROOT] = imx_clk_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0);
|
||||
clks[IMX8MN_CLK_SDMA3_ROOT] = imx_clk_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0);
|
||||
clks[IMX8MN_CLK_SAI7_ROOT] = imx_clk_gate2_shared2("sai7_root_clk", "sai7", base + 0x4650, 0, &share_count_sai7);
|
||||
|
||||
clks[IMX8MN_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
|
||||
|
||||
clks[IMX8MN_CLK_ARM] = imx_clk_cpu("arm", "arm_a53_div",
|
||||
clks[IMX8MN_CLK_A53_DIV],
|
||||
clks[IMX8MN_CLK_A53_SRC],
|
||||
clks[IMX8MN_ARM_PLL_OUT],
|
||||
clks[IMX8MN_CLK_24M]);
|
||||
|
||||
imx_check_clocks(clks, ARRAY_SIZE(clks));
|
||||
|
||||
clk_data.clks = clks;
|
||||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to register clks for i.MX8MN\n");
|
||||
goto unregister_clks;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
|
||||
return 0;
|
||||
|
||||
unregister_clks:
|
||||
imx_unregister_clocks(clks, ARRAY_SIZE(clks));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id imx8mn_clk_of_match[] = {
|
||||
{ .compatible = "fsl,imx8mn-ccm" },
|
||||
{ /* Sentinel */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, imx8mn_clk_of_match);
|
||||
|
||||
static struct platform_driver imx8mn_clk_driver = {
|
||||
.probe = imx8mn_clocks_probe,
|
||||
.driver = {
|
||||
.name = "imx8mn-ccm",
|
||||
.of_match_table = of_match_ptr(imx8mn_clk_of_match),
|
||||
},
|
||||
};
|
||||
module_platform_driver(imx8mn_clk_driver);
|
||||
@ -41,34 +41,34 @@ static const char * const dram_pll_out_sels[] = {"dram_pll1_ref_sel", };
|
||||
|
||||
/* CCM ROOT */
|
||||
static const char * const imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
|
||||
"sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll2_out", };
|
||||
"sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll_out", };
|
||||
|
||||
static const char * const imx8mq_arm_m4_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_250m", "sys1_pll_266m",
|
||||
"sys1_pll_800m", "audio_pll1_out", "video_pll1_out", "sys3_pll2_out", };
|
||||
"sys1_pll_800m", "audio_pll1_out", "video_pll1_out", "sys3_pll_out", };
|
||||
|
||||
static const char * const imx8mq_vpu_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
|
||||
"sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "vpu_pll_out", };
|
||||
|
||||
static const char * const imx8mq_gpu_core_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll2_out",
|
||||
static const char * const imx8mq_gpu_core_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll_out",
|
||||
"sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_gpu_shader_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll2_out",
|
||||
static const char * const imx8mq_gpu_shader_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll_out",
|
||||
"sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_main_axi_sels[] = {"osc_25m", "sys2_pll_333m", "sys1_pll_800m", "sys2_pll_250m",
|
||||
"sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "sys1_pll_100m",};
|
||||
|
||||
static const char * const imx8mq_enet_axi_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_250m",
|
||||
"sys2_pll_200m", "audio_pll1_out", "video_pll1_out", "sys3_pll2_out", };
|
||||
"sys2_pll_200m", "audio_pll1_out", "video_pll1_out", "sys3_pll_out", };
|
||||
|
||||
static const char * const imx8mq_nand_usdhc_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_200m",
|
||||
"sys1_pll_133m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll1_out", };
|
||||
"sys1_pll_133m", "sys3_pll_out", "sys2_pll_250m", "audio_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_vpu_bus_sels[] = {"osc_25m", "sys1_pll_800m", "vpu_pll_out", "audio_pll2_out", "sys3_pll2_out", "sys2_pll_1000m", "sys2_pll_200m", "sys1_pll_100m", };
|
||||
static const char * const imx8mq_vpu_bus_sels[] = {"osc_25m", "sys1_pll_800m", "vpu_pll_out", "audio_pll2_out", "sys3_pll_out", "sys2_pll_1000m", "sys2_pll_200m", "sys1_pll_100m", };
|
||||
|
||||
static const char * const imx8mq_disp_axi_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll2_out", "sys1_pll_400m", "audio_pll2_out", "clk_ext1", "clk_ext4", };
|
||||
static const char * const imx8mq_disp_axi_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll_out", "sys1_pll_400m", "audio_pll2_out", "clk_ext1", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mq_disp_apb_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll2_out",
|
||||
static const char * const imx8mq_disp_apb_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll_out",
|
||||
"sys1_pll_40m", "audio_pll2_out", "clk_ext1", "clk_ext3", };
|
||||
|
||||
static const char * const imx8mq_disp_rtrm_sels[] = {"osc_25m", "sys1_pll_800m", "sys2_pll_200m", "sys1_pll_400m",
|
||||
@ -77,53 +77,53 @@ static const char * const imx8mq_disp_rtrm_sels[] = {"osc_25m", "sys1_pll_800m",
|
||||
static const char * const imx8mq_usb_bus_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_100m",
|
||||
"sys2_pll_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_gpu_axi_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll2_out", "sys2_pll_1000m",
|
||||
static const char * const imx8mq_gpu_axi_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll_out", "sys2_pll_1000m",
|
||||
"audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_gpu_ahb_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll2_out", "sys2_pll_1000m",
|
||||
static const char * const imx8mq_gpu_ahb_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll_out", "sys2_pll_1000m",
|
||||
"audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_noc_sels[] = {"osc_25m", "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_1000m", "sys2_pll_500m",
|
||||
static const char * const imx8mq_noc_sels[] = {"osc_25m", "sys1_pll_800m", "sys3_pll_out", "sys2_pll_1000m", "sys2_pll_500m",
|
||||
"audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_noc_apb_sels[] = {"osc_25m", "sys1_pll_400m", "sys3_pll2_out", "sys2_pll_333m", "sys2_pll_200m",
|
||||
static const char * const imx8mq_noc_apb_sels[] = {"osc_25m", "sys1_pll_400m", "sys3_pll_out", "sys2_pll_333m", "sys2_pll_200m",
|
||||
"sys1_pll_800m", "audio_pll1_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_ahb_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_800m", "sys1_pll_400m",
|
||||
"sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", };
|
||||
"sys2_pll_125m", "sys3_pll_out", "audio_pll1_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_audio_ahb_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_1000m",
|
||||
"sys2_pll_166m", "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", };
|
||||
"sys2_pll_166m", "sys3_pll_out", "audio_pll1_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_dsi_ahb_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out"};
|
||||
"sys2_pll_1000m", "sys3_pll_out", "clk_ext3", "audio_pll2_out"};
|
||||
|
||||
static const char * const imx8mq_dram_alt_sels[] = {"osc_25m", "sys1_pll_800m", "sys1_pll_100m", "sys2_pll_500m",
|
||||
"sys2_pll_250m", "sys1_pll_400m", "audio_pll1_out", "sys1_pll_266m", };
|
||||
|
||||
static const char * const imx8mq_dram_apb_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
|
||||
"sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
|
||||
"sys1_pll_800m", "sys3_pll_out", "sys2_pll_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_vpu_g1_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", };
|
||||
static const char * const imx8mq_vpu_g1_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll_out", "audio_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_vpu_g2_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", };
|
||||
static const char * const imx8mq_vpu_g2_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll_out", "audio_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_disp_dtrc_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll2_out", "audio_pll2_out", };
|
||||
static const char * const imx8mq_disp_dtrc_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_disp_dc8000_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll2_out", "audio_pll2_out", };
|
||||
static const char * const imx8mq_disp_dc8000_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_pcie1_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m",
|
||||
"sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll2_out", };
|
||||
"sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll_out", };
|
||||
|
||||
static const char * const imx8mq_pcie1_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll2_out",
|
||||
static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll_out",
|
||||
"sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", };
|
||||
|
||||
static const char * const imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", };
|
||||
static const char * const imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll_out", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mq_lcdif_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", };
|
||||
static const char * const imx8mq_lcdif_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll_out", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mq_sai1_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext1", "clk_ext2", };
|
||||
|
||||
@ -151,40 +151,40 @@ static const char * const imx8mq_enet_phy_sels[] = {"osc_25m", "sys2_pll_50m", "
|
||||
"audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_nand_sels[] = {"osc_25m", "sys2_pll_500m", "audio_pll1_out", "sys1_pll_400m",
|
||||
"audio_pll2_out", "sys3_pll2_out", "sys2_pll_250m", "video_pll1_out", };
|
||||
"audio_pll2_out", "sys3_pll_out", "sys2_pll_250m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_qspi_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
|
||||
"audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", };
|
||||
"audio_pll2_out", "sys1_pll_266m", "sys3_pll_out", "sys1_pll_100m", };
|
||||
|
||||
static const char * const imx8mq_usdhc1_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
|
||||
"audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", };
|
||||
"audio_pll2_out", "sys1_pll_266m", "sys3_pll_out", "sys1_pll_100m", };
|
||||
|
||||
static const char * const imx8mq_usdhc2_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
|
||||
"audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", };
|
||||
"audio_pll2_out", "sys1_pll_266m", "sys3_pll_out", "sys1_pll_100m", };
|
||||
|
||||
static const char * const imx8mq_i2c1_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
|
||||
static const char * const imx8mq_i2c1_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
|
||||
|
||||
static const char * const imx8mq_i2c2_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
|
||||
static const char * const imx8mq_i2c2_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
|
||||
|
||||
static const char * const imx8mq_i2c3_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
|
||||
static const char * const imx8mq_i2c3_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
|
||||
|
||||
static const char * const imx8mq_i2c4_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
|
||||
static const char * const imx8mq_i2c4_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
|
||||
|
||||
static const char * const imx8mq_uart1_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
|
||||
"sys3_pll2_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
|
||||
"sys3_pll_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_uart2_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
|
||||
"sys3_pll2_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
|
||||
"sys3_pll_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_uart3_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
|
||||
"sys3_pll2_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
|
||||
"sys3_pll_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_uart4_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
|
||||
"sys3_pll2_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
|
||||
"sys3_pll_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_usb_core_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m",
|
||||
"sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
|
||||
@ -196,79 +196,79 @@ static const char * const imx8mq_gic_sels[] = {"osc_25m", "sys2_pll_200m", "sys1
|
||||
"sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out" };
|
||||
|
||||
static const char * const imx8mq_ecspi1_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
|
||||
"sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
|
||||
"sys1_pll_800m", "sys3_pll_out", "sys2_pll_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_ecspi2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
|
||||
"sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
|
||||
"sys1_pll_800m", "sys3_pll_out", "sys2_pll_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_pwm1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
|
||||
"sys3_pll2_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
|
||||
"sys3_pll_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_pwm2_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
|
||||
"sys3_pll2_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
|
||||
"sys3_pll_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_pwm3_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
|
||||
"sys3_pll2_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
|
||||
"sys3_pll_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_pwm4_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
|
||||
"sys3_pll2_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
|
||||
"sys3_pll_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_gpt1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_400m", "sys1_pll_40m",
|
||||
"sys1_pll_80m", "audio_pll1_out", "clk_ext1", };
|
||||
|
||||
static const char * const imx8mq_wdog_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_160m", "vpu_pll_out",
|
||||
"sys2_pll_125m", "sys3_pll2_out", "sys1_pll_80m", "sys2_pll_166m", };
|
||||
"sys2_pll_125m", "sys3_pll_out", "sys1_pll_80m", "sys2_pll_166m", };
|
||||
|
||||
static const char * const imx8mq_wrclk_sels[] = {"osc_25m", "sys1_pll_40m", "vpu_pll_out", "sys3_pll2_out", "sys2_pll_200m",
|
||||
static const char * const imx8mq_wrclk_sels[] = {"osc_25m", "sys1_pll_40m", "vpu_pll_out", "sys3_pll_out", "sys2_pll_200m",
|
||||
"sys1_pll_266m", "sys2_pll_500m", "sys1_pll_100m", };
|
||||
|
||||
static const char * const imx8mq_dsi_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_dsi_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_dsi_dbi_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_100m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_dsi_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_csi1_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_csi1_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_csi2_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_csi2_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_pcie2_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m",
|
||||
"sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll2_out", };
|
||||
"sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll_out", };
|
||||
|
||||
static const char * const imx8mq_pcie2_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1",
|
||||
"clk_ext2", "clk_ext3", "clk_ext4", "sys1_pll_400m", };
|
||||
|
||||
static const char * const imx8mq_pcie2_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll2_out",
|
||||
static const char * const imx8mq_pcie2_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll_out",
|
||||
"sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", };
|
||||
|
||||
static const char * const imx8mq_ecspi3_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
|
||||
"sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
|
||||
"sys1_pll_800m", "sys3_pll_out", "sys2_pll_250m", "audio_pll2_out", };
|
||||
static const char * const imx8mq_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
|
||||
|
||||
static const char * const imx8mq_clko1_sels[] = {"osc_25m", "sys1_pll_800m", "osc_27m", "sys1_pll_200m",
|
||||
"audio_pll2_out", "sys2_pll_500m", "vpu_pll_out", "sys1_pll_80m", };
|
||||
static const char * const imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m",
|
||||
"sys3_pll2_out", "audio_pll1_out", "video_pll1_out", "ckil", };
|
||||
"sys3_pll_out", "audio_pll1_out", "video_pll1_out", "ckil", };
|
||||
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
@ -406,7 +406,8 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
||||
clks[IMX8MQ_CLK_NOC_APB] = imx8m_clk_composite_critical("noc_apb", imx8mq_noc_apb_sels, base + 0x8d80);
|
||||
|
||||
/* AHB */
|
||||
clks[IMX8MQ_CLK_AHB] = imx8m_clk_composite("ahb", imx8mq_ahb_sels, base + 0x9000);
|
||||
/* AHB clock is used by the AHB bus therefore marked as critical */
|
||||
clks[IMX8MQ_CLK_AHB] = imx8m_clk_composite_critical("ahb", imx8mq_ahb_sels, base + 0x9000);
|
||||
clks[IMX8MQ_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mq_audio_ahb_sels, base + 0x9100);
|
||||
|
||||
/* IPG */
|
||||
@ -523,8 +524,8 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
||||
clks[IMX8MQ_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
|
||||
clks[IMX8MQ_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
|
||||
clks[IMX8MQ_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
|
||||
clks[IMX8MQ_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0);
|
||||
clks[IMX8MQ_CLK_USB2_CTRL_ROOT] = imx_clk_gate4("usb2_ctrl_root_clk", "usb_core_ref", base + 0x44e0, 0);
|
||||
clks[IMX8MQ_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0);
|
||||
clks[IMX8MQ_CLK_USB2_CTRL_ROOT] = imx_clk_gate4("usb2_ctrl_root_clk", "usb_bus", base + 0x44e0, 0);
|
||||
clks[IMX8MQ_CLK_USB1_PHY_ROOT] = imx_clk_gate4("usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0);
|
||||
clks[IMX8MQ_CLK_USB2_PHY_ROOT] = imx_clk_gate4("usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0);
|
||||
clks[IMX8MQ_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
|
||||
@ -539,7 +540,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
||||
clks[IMX8MQ_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_dcss);
|
||||
clks[IMX8MQ_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_dcss);
|
||||
clks[IMX8MQ_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_dcss);
|
||||
clks[IMX8MQ_CLK_TMU_ROOT] = imx_clk_gate4_flags("tmu_root_clk", "ipg_root", base + 0x4620, 0, CLK_IS_CRITICAL);
|
||||
clks[IMX8MQ_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0);
|
||||
clks[IMX8MQ_CLK_VPU_DEC_ROOT] = imx_clk_gate2_flags("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
|
||||
clks[IMX8MQ_CLK_CSI1_ROOT] = imx_clk_gate4("csi1_root_clk", "csi1_core", base + 0x4650, 0);
|
||||
clks[IMX8MQ_CLK_CSI2_ROOT] = imx_clk_gate4("csi2_root_clk", "csi2_core", base + 0x4660, 0);
|
||||
@ -561,10 +562,18 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
||||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
|
||||
err = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
WARN_ON(err);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "failed to register clks for i.MX8MQ\n");
|
||||
goto unregister_clks;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
|
||||
return 0;
|
||||
|
||||
unregister_clks:
|
||||
imx_unregister_clocks(clks, ARRAY_SIZE(clks));
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
@ -72,6 +72,11 @@ static const struct imx8qxp_lpcg_data imx8qxp_lpcg_adma[] = {
|
||||
{ IMX_ADMA_LPCG_I2C2_CLK, "i2c2_lpcg_clk", "i2c2_clk", 0, ADMA_LPI2C_2_LPCG, 0, 0, },
|
||||
{ IMX_ADMA_LPCG_I2C3_IPG_CLK, "i2c3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_3_LPCG, 16, 0, },
|
||||
{ IMX_ADMA_LPCG_I2C3_CLK, "i2c3_lpcg_clk", "i2c3_clk", 0, ADMA_LPI2C_3_LPCG, 0, 0, },
|
||||
|
||||
{ IMX_ADMA_LPCG_DSP_CORE_CLK, "dsp_lpcg_core_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 28, 0, },
|
||||
{ IMX_ADMA_LPCG_DSP_IPG_CLK, "dsp_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 20, 0, },
|
||||
{ IMX_ADMA_LPCG_DSP_ADB_CLK, "dsp_lpcg_adb_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 16, 0, },
|
||||
{ IMX_ADMA_LPCG_OCRAM_IPG_CLK, "ocram_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_OCRAM_LPCG, 16, 0, },
|
||||
};
|
||||
|
||||
static const struct imx8qxp_ss_lpcg imx8qxp_ss_adma = {
|
||||
|
||||
@ -14,6 +14,14 @@
|
||||
|
||||
DEFINE_SPINLOCK(imx_ccm_lock);
|
||||
|
||||
void imx_unregister_clocks(struct clk *clks[], unsigned int count)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < count; i++)
|
||||
clk_unregister(clks[i]);
|
||||
}
|
||||
|
||||
void __init imx_mmdc_mask_handshake(void __iomem *ccm_base,
|
||||
unsigned int chn)
|
||||
{
|
||||
|
||||
@ -10,8 +10,8 @@ extern spinlock_t imx_ccm_lock;
|
||||
void imx_check_clocks(struct clk *clks[], unsigned int count);
|
||||
void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
|
||||
void imx_register_uart_clocks(struct clk ** const clks[]);
|
||||
void imx_register_uart_clocks_hws(struct clk_hw ** const hws[]);
|
||||
void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn);
|
||||
void imx_unregister_clocks(struct clk *clks[], unsigned int count);
|
||||
|
||||
extern void imx_cscmr1_fixup(u32 *val);
|
||||
|
||||
@ -50,12 +50,6 @@ struct imx_pll14xx_clk {
|
||||
int flags;
|
||||
};
|
||||
|
||||
#define imx_clk_busy_divider(name, parent_name, reg, shift, width, busy_reg, busy_shift) \
|
||||
imx_clk_hw_busy_divider(name, parent_name, reg, shift, width, busy_reg, busy_shift)->clk
|
||||
|
||||
#define imx_clk_busy_mux(name, reg, shift, width, busy_reg, busy_shift, parent_names, num_parents) \
|
||||
imx_clk_hw_busy_mux(name, reg, shift, width, busy_reg, busy_shift, parent_names, num_parents)->clk
|
||||
|
||||
#define imx_clk_cpu(name, parent_name, div, mux, pll, step) \
|
||||
imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)->clk
|
||||
|
||||
@ -73,15 +67,6 @@ struct imx_pll14xx_clk {
|
||||
#define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \
|
||||
imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask)->clk
|
||||
|
||||
#define imx_clk_fixup_divider(name, parent, reg, shift, width, fixup) \
|
||||
imx_clk_hw_fixup_divider(name, parent, reg, shift, width, fixup)->clk
|
||||
|
||||
#define imx_clk_fixup_mux(name, reg, shift, width, parents, num_parents, fixup) \
|
||||
imx_clk_hw_fixup_mux(name, reg, shift, width, parents, num_parents, fixup)->clk
|
||||
|
||||
#define imx_clk_mux_ldb(name, reg, shift, width, parents, num_parents) \
|
||||
imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents)->clk
|
||||
|
||||
#define imx_clk_fixed_factor(name, parent, mult, div) \
|
||||
imx_clk_hw_fixed_factor(name, parent, mult, div)->clk
|
||||
|
||||
@ -91,21 +76,12 @@ struct imx_pll14xx_clk {
|
||||
#define imx_clk_gate_dis(name, parent, reg, shift) \
|
||||
imx_clk_hw_gate_dis(name, parent, reg, shift)->clk
|
||||
|
||||
#define imx_clk_gate_dis_flags(name, parent, reg, shift, flags) \
|
||||
imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags)->clk
|
||||
|
||||
#define imx_clk_gate_flags(name, parent, reg, shift, flags) \
|
||||
imx_clk_hw_gate_flags(name, parent, reg, shift, flags)->clk
|
||||
|
||||
#define imx_clk_gate2(name, parent, reg, shift) \
|
||||
imx_clk_hw_gate2(name, parent, reg, shift)->clk
|
||||
|
||||
#define imx_clk_gate2_flags(name, parent, reg, shift, flags) \
|
||||
imx_clk_hw_gate2_flags(name, parent, reg, shift, flags)->clk
|
||||
|
||||
#define imx_clk_gate2_shared(name, parent, reg, shift, share_count) \
|
||||
imx_clk_hw_gate2_shared(name, parent, reg, shift, share_count)->clk
|
||||
|
||||
#define imx_clk_gate2_shared2(name, parent, reg, shift, share_count) \
|
||||
imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count)->clk
|
||||
|
||||
@ -153,6 +129,23 @@ enum imx_pllv3_type {
|
||||
struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
|
||||
const char *parent_name, void __iomem *base, u32 div_mask);
|
||||
|
||||
#define PLL_1416X_RATE(_rate, _m, _p, _s) \
|
||||
{ \
|
||||
.rate = (_rate), \
|
||||
.mdiv = (_m), \
|
||||
.pdiv = (_p), \
|
||||
.sdiv = (_s), \
|
||||
}
|
||||
|
||||
#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
|
||||
{ \
|
||||
.rate = (_rate), \
|
||||
.mdiv = (_m), \
|
||||
.pdiv = (_p), \
|
||||
.sdiv = (_s), \
|
||||
.kdiv = (_k), \
|
||||
}
|
||||
|
||||
struct clk_hw *imx_clk_pllv4(const char *name, const char *parent_name,
|
||||
void __iomem *base);
|
||||
|
||||
|
||||
@ -283,7 +283,11 @@
|
||||
#define IMX_ADMA_LPCG_PWM_IPG_CLK 38
|
||||
#define IMX_ADMA_LPCG_LCD_PIX_CLK 39
|
||||
#define IMX_ADMA_LPCG_LCD_APB_CLK 40
|
||||
#define IMX_ADMA_LPCG_DSP_ADB_CLK 41
|
||||
#define IMX_ADMA_LPCG_DSP_IPG_CLK 42
|
||||
#define IMX_ADMA_LPCG_DSP_CORE_CLK 43
|
||||
#define IMX_ADMA_LPCG_OCRAM_IPG_CLK 44
|
||||
|
||||
#define IMX_ADMA_LPCG_CLK_END 41
|
||||
#define IMX_ADMA_LPCG_CLK_END 45
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX_H */
|
||||
|
||||
216
include/dt-bindings/clock/imx8mn-clock.h
Normal file
216
include/dt-bindings/clock/imx8mn-clock.h
Normal file
@ -0,0 +1,216 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright 2018-2019 NXP
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H
|
||||
#define __DT_BINDINGS_CLOCK_IMX8MN_H
|
||||
|
||||
#define IMX8MN_CLK_DUMMY 0
|
||||
#define IMX8MN_CLK_32K 1
|
||||
#define IMX8MN_CLK_24M 2
|
||||
#define IMX8MN_OSC_HDMI_CLK 3
|
||||
#define IMX8MN_CLK_EXT1 4
|
||||
#define IMX8MN_CLK_EXT2 5
|
||||
#define IMX8MN_CLK_EXT3 6
|
||||
#define IMX8MN_CLK_EXT4 7
|
||||
#define IMX8MN_AUDIO_PLL1_REF_SEL 8
|
||||
#define IMX8MN_AUDIO_PLL2_REF_SEL 9
|
||||
#define IMX8MN_VIDEO_PLL1_REF_SEL 10
|
||||
#define IMX8MN_DRAM_PLL_REF_SEL 11
|
||||
#define IMX8MN_GPU_PLL_REF_SEL 12
|
||||
#define IMX8MN_VPU_PLL_REF_SEL 13
|
||||
#define IMX8MN_ARM_PLL_REF_SEL 14
|
||||
#define IMX8MN_SYS_PLL1_REF_SEL 15
|
||||
#define IMX8MN_SYS_PLL2_REF_SEL 16
|
||||
#define IMX8MN_SYS_PLL3_REF_SEL 17
|
||||
#define IMX8MN_AUDIO_PLL1 18
|
||||
#define IMX8MN_AUDIO_PLL2 19
|
||||
#define IMX8MN_VIDEO_PLL1 20
|
||||
#define IMX8MN_DRAM_PLL 21
|
||||
#define IMX8MN_GPU_PLL 22
|
||||
#define IMX8MN_VPU_PLL 23
|
||||
#define IMX8MN_ARM_PLL 24
|
||||
#define IMX8MN_SYS_PLL1 25
|
||||
#define IMX8MN_SYS_PLL2 26
|
||||
#define IMX8MN_SYS_PLL3 27
|
||||
#define IMX8MN_AUDIO_PLL1_BYPASS 28
|
||||
#define IMX8MN_AUDIO_PLL2_BYPASS 29
|
||||
#define IMX8MN_VIDEO_PLL1_BYPASS 30
|
||||
#define IMX8MN_DRAM_PLL_BYPASS 31
|
||||
#define IMX8MN_GPU_PLL_BYPASS 32
|
||||
#define IMX8MN_VPU_PLL_BYPASS 33
|
||||
#define IMX8MN_ARM_PLL_BYPASS 34
|
||||
#define IMX8MN_SYS_PLL1_BYPASS 35
|
||||
#define IMX8MN_SYS_PLL2_BYPASS 36
|
||||
#define IMX8MN_SYS_PLL3_BYPASS 37
|
||||
#define IMX8MN_AUDIO_PLL1_OUT 38
|
||||
#define IMX8MN_AUDIO_PLL2_OUT 39
|
||||
#define IMX8MN_VIDEO_PLL1_OUT 40
|
||||
#define IMX8MN_DRAM_PLL_OUT 41
|
||||
#define IMX8MN_GPU_PLL_OUT 42
|
||||
#define IMX8MN_VPU_PLL_OUT 43
|
||||
#define IMX8MN_ARM_PLL_OUT 44
|
||||
#define IMX8MN_SYS_PLL1_OUT 45
|
||||
#define IMX8MN_SYS_PLL2_OUT 46
|
||||
#define IMX8MN_SYS_PLL3_OUT 47
|
||||
#define IMX8MN_SYS_PLL1_40M 48
|
||||
#define IMX8MN_SYS_PLL1_80M 49
|
||||
#define IMX8MN_SYS_PLL1_100M 50
|
||||
#define IMX8MN_SYS_PLL1_133M 51
|
||||
#define IMX8MN_SYS_PLL1_160M 52
|
||||
#define IMX8MN_SYS_PLL1_200M 53
|
||||
#define IMX8MN_SYS_PLL1_266M 54
|
||||
#define IMX8MN_SYS_PLL1_400M 55
|
||||
#define IMX8MN_SYS_PLL1_800M 56
|
||||
#define IMX8MN_SYS_PLL2_50M 57
|
||||
#define IMX8MN_SYS_PLL2_100M 58
|
||||
#define IMX8MN_SYS_PLL2_125M 59
|
||||
#define IMX8MN_SYS_PLL2_166M 60
|
||||
#define IMX8MN_SYS_PLL2_200M 61
|
||||
#define IMX8MN_SYS_PLL2_250M 62
|
||||
#define IMX8MN_SYS_PLL2_333M 63
|
||||
#define IMX8MN_SYS_PLL2_500M 64
|
||||
#define IMX8MN_SYS_PLL2_1000M 65
|
||||
|
||||
/* CORE CLOCK ROOT */
|
||||
#define IMX8MN_CLK_A53_SRC 66
|
||||
#define IMX8MN_CLK_GPU_CORE_SRC 67
|
||||
#define IMX8MN_CLK_GPU_SHADER_SRC 68
|
||||
#define IMX8MN_CLK_A53_CG 69
|
||||
#define IMX8MN_CLK_GPU_CORE_CG 70
|
||||
#define IMX8MN_CLK_GPU_SHADER_CG 71
|
||||
#define IMX8MN_CLK_A53_DIV 72
|
||||
#define IMX8MN_CLK_GPU_CORE_DIV 73
|
||||
#define IMX8MN_CLK_GPU_SHADER_DIV 74
|
||||
|
||||
/* BUS CLOCK ROOT */
|
||||
#define IMX8MN_CLK_MAIN_AXI 75
|
||||
#define IMX8MN_CLK_ENET_AXI 76
|
||||
#define IMX8MN_CLK_NAND_USDHC_BUS 77
|
||||
#define IMX8MN_CLK_DISP_AXI 78
|
||||
#define IMX8MN_CLK_DISP_APB 79
|
||||
#define IMX8MN_CLK_USB_BUS 80
|
||||
#define IMX8MN_CLK_GPU_AXI 81
|
||||
#define IMX8MN_CLK_GPU_AHB 82
|
||||
#define IMX8MN_CLK_NOC 83
|
||||
#define IMX8MN_CLK_AHB 84
|
||||
#define IMX8MN_CLK_AUDIO_AHB 85
|
||||
|
||||
/* IPG CLOCK ROOT */
|
||||
#define IMX8MN_CLK_IPG_ROOT 86
|
||||
#define IMX8MN_CLK_IPG_AUDIO_ROOT 87
|
||||
|
||||
/* IP */
|
||||
#define IMX8MN_CLK_DRAM_CORE 88
|
||||
#define IMX8MN_CLK_DRAM_ALT 89
|
||||
#define IMX8MN_CLK_DRAM_APB 90
|
||||
#define IMX8MN_CLK_DRAM_ALT_ROOT 91
|
||||
#define IMX8MN_CLK_DISP_PIXEL 92
|
||||
#define IMX8MN_CLK_SAI2 93
|
||||
#define IMX8MN_CLK_SAI3 94
|
||||
#define IMX8MN_CLK_SAI5 95
|
||||
#define IMX8MN_CLK_SAI6 96
|
||||
#define IMX8MN_CLK_SPDIF1 97
|
||||
#define IMX8MN_CLK_ENET_REF 98
|
||||
#define IMX8MN_CLK_ENET_TIMER 99
|
||||
#define IMX8MN_CLK_ENET_PHY_REF 100
|
||||
#define IMX8MN_CLK_NAND 101
|
||||
#define IMX8MN_CLK_QSPI 102
|
||||
#define IMX8MN_CLK_USDHC1 103
|
||||
#define IMX8MN_CLK_USDHC2 104
|
||||
#define IMX8MN_CLK_I2C1 105
|
||||
#define IMX8MN_CLK_I2C2 106
|
||||
#define IMX8MN_CLK_I2C3 107
|
||||
#define IMX8MN_CLK_I2C4 118
|
||||
#define IMX8MN_CLK_UART1 119
|
||||
#define IMX8MN_CLK_UART2 110
|
||||
#define IMX8MN_CLK_UART3 111
|
||||
#define IMX8MN_CLK_UART4 112
|
||||
#define IMX8MN_CLK_USB_CORE_REF 113
|
||||
#define IMX8MN_CLK_USB_PHY_REF 114
|
||||
#define IMX8MN_CLK_ECSPI1 115
|
||||
#define IMX8MN_CLK_ECSPI2 116
|
||||
#define IMX8MN_CLK_PWM1 117
|
||||
#define IMX8MN_CLK_PWM2 118
|
||||
#define IMX8MN_CLK_PWM3 119
|
||||
#define IMX8MN_CLK_PWM4 120
|
||||
#define IMX8MN_CLK_WDOG 121
|
||||
#define IMX8MN_CLK_WRCLK 122
|
||||
#define IMX8MN_CLK_CLKO1 123
|
||||
#define IMX8MN_CLK_CLKO2 124
|
||||
#define IMX8MN_CLK_DSI_CORE 125
|
||||
#define IMX8MN_CLK_DSI_PHY_REF 126
|
||||
#define IMX8MN_CLK_DSI_DBI 127
|
||||
#define IMX8MN_CLK_USDHC3 128
|
||||
#define IMX8MN_CLK_CAMERA_PIXEL 129
|
||||
#define IMX8MN_CLK_CSI1_PHY_REF 130
|
||||
#define IMX8MN_CLK_CSI2_PHY_REF 131
|
||||
#define IMX8MN_CLK_CSI2_ESC 132
|
||||
#define IMX8MN_CLK_ECSPI3 133
|
||||
#define IMX8MN_CLK_PDM 134
|
||||
#define IMX8MN_CLK_SAI7 135
|
||||
|
||||
#define IMX8MN_CLK_ECSPI1_ROOT 136
|
||||
#define IMX8MN_CLK_ECSPI2_ROOT 137
|
||||
#define IMX8MN_CLK_ECSPI3_ROOT 138
|
||||
#define IMX8MN_CLK_ENET1_ROOT 139
|
||||
#define IMX8MN_CLK_GPIO1_ROOT 140
|
||||
#define IMX8MN_CLK_GPIO2_ROOT 141
|
||||
#define IMX8MN_CLK_GPIO3_ROOT 142
|
||||
#define IMX8MN_CLK_GPIO4_ROOT 143
|
||||
#define IMX8MN_CLK_GPIO5_ROOT 144
|
||||
#define IMX8MN_CLK_I2C1_ROOT 145
|
||||
#define IMX8MN_CLK_I2C2_ROOT 146
|
||||
#define IMX8MN_CLK_I2C3_ROOT 147
|
||||
#define IMX8MN_CLK_I2C4_ROOT 148
|
||||
#define IMX8MN_CLK_MU_ROOT 149
|
||||
#define IMX8MN_CLK_OCOTP_ROOT 150
|
||||
#define IMX8MN_CLK_PWM1_ROOT 151
|
||||
#define IMX8MN_CLK_PWM2_ROOT 152
|
||||
#define IMX8MN_CLK_PWM3_ROOT 153
|
||||
#define IMX8MN_CLK_PWM4_ROOT 154
|
||||
#define IMX8MN_CLK_QSPI_ROOT 155
|
||||
#define IMX8MN_CLK_NAND_ROOT 156
|
||||
#define IMX8MN_CLK_SAI2_ROOT 157
|
||||
#define IMX8MN_CLK_SAI2_IPG 158
|
||||
#define IMX8MN_CLK_SAI3_ROOT 159
|
||||
#define IMX8MN_CLK_SAI3_IPG 160
|
||||
#define IMX8MN_CLK_SAI5_ROOT 161
|
||||
#define IMX8MN_CLK_SAI5_IPG 162
|
||||
#define IMX8MN_CLK_SAI6_ROOT 163
|
||||
#define IMX8MN_CLK_SAI6_IPG 164
|
||||
#define IMX8MN_CLK_SAI7_ROOT 165
|
||||
#define IMX8MN_CLK_SAI7_IPG 166
|
||||
#define IMX8MN_CLK_SDMA1_ROOT 167
|
||||
#define IMX8MN_CLK_SDMA2_ROOT 168
|
||||
#define IMX8MN_CLK_UART1_ROOT 169
|
||||
#define IMX8MN_CLK_UART2_ROOT 170
|
||||
#define IMX8MN_CLK_UART3_ROOT 171
|
||||
#define IMX8MN_CLK_UART4_ROOT 172
|
||||
#define IMX8MN_CLK_USB1_CTRL_ROOT 173
|
||||
#define IMX8MN_CLK_USDHC1_ROOT 174
|
||||
#define IMX8MN_CLK_USDHC2_ROOT 175
|
||||
#define IMX8MN_CLK_WDOG1_ROOT 176
|
||||
#define IMX8MN_CLK_WDOG2_ROOT 177
|
||||
#define IMX8MN_CLK_WDOG3_ROOT 178
|
||||
#define IMX8MN_CLK_GPU_BUS_ROOT 179
|
||||
#define IMX8MN_CLK_ASRC_ROOT 180
|
||||
#define IMX8MN_CLK_GPU3D_ROOT 181
|
||||
#define IMX8MN_CLK_PDM_ROOT 182
|
||||
#define IMX8MN_CLK_PDM_IPG 183
|
||||
#define IMX8MN_CLK_DISP_AXI_ROOT 184
|
||||
#define IMX8MN_CLK_DISP_APB_ROOT 185
|
||||
#define IMX8MN_CLK_DISP_PIXEL_ROOT 186
|
||||
#define IMX8MN_CLK_CAMERA_PIXEL_ROOT 187
|
||||
#define IMX8MN_CLK_USDHC3_ROOT 188
|
||||
#define IMX8MN_CLK_SDMA3_ROOT 189
|
||||
#define IMX8MN_CLK_TMU_ROOT 190
|
||||
#define IMX8MN_CLK_ARM 191
|
||||
#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192
|
||||
#define IMX8MN_CLK_GPU_CORE_ROOT 193
|
||||
#define IMX8MN_CLK_GIC 194
|
||||
|
||||
#define IMX8MN_CLK_END 195
|
||||
|
||||
#endif
|
||||
Loading…
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Reference in New Issue
Block a user