Qualcomm Device Tree Changes for v4.12
* Add Coresight components for MSM8974 * Fixup MSM8974 ADSP XO clk and add RPMCC node * Fix typo in APQ8060 * Add SDCs on MSM8660 * Revert MSM8974 USB gadget change due to issues -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJY5tTkAAoJEFKiBbHx2RXVq7AQAMkcalh0NImOfm4uy4alB0ku +3Hr7vkAajQY1MHOqJMdqqSytiycC6TEF8q6ihRuAYK2dWeNARX+FB0Fds+H2ndE IgodHQWqUVKoBa+MTarav6nc9ajb9ToPtbpnhkM36k3eVfGhzLQ2NHd18gpfdEYV RvTA3RZCzHux+anzmJgLcANqEDAfIRjzH4F9hQ1gzPPqiNXTReJYeGXk1eMro76X cx49w0R4jQEgo4pstmYHkJ7wCL0XLz8swNZFlQx1f5qBd010IPW8zeX38rmuRF9M zf54Va57gi8mD+SU+6mGs3OMtgztDDjvtwbef45dweOLxNZYMdh221UJz2/MIt8n mF8Lc4M+SLgy9DbwmOcFtOtYKIZv7/19stH2Yv9/nVMkRYNaQLIgXfK9liTgesj2 65JAFiQGPnA66KLAqJbHeMp3iEAUVeGCigZHNMYq0eYxX0lrQRF+7LYokVtEcJhu L1zbBNJHuuhCdL4eVnheD3j3jab9IdEfEdxG4RlsBuVwT0bIYSslL6mwZIKwnuTS PFbO8t9u/bLyujrbxnqO/aHsGH0AA6yUosb77HHRpkyZZo/nMRtM3eNpaX5n4WAV CSbQzRp2IHTLU+QBCaVQvZc+xi4e0veXG7EkYRi3D/+QH7fG8Ix7jxGNJpsAZtol me85BP13RaJ2dakcRpKj =N6rc -----END PGP SIGNATURE----- Merge tag 'qcom-dts-for-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt Qualcomm Device Tree Changes for v4.12 * Add Coresight components for MSM8974 * Fixup MSM8974 ADSP XO clk and add RPMCC node * Fix typo in APQ8060 * Add SDCs on MSM8660 * Revert MSM8974 USB gadget change due to issues * tag 'qcom-dts-for-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: Revert "ARM: dts: qcom: msm8974: Add USB gadget nodes" ARM: dts: qcom: msm8974: Add RPMCC DT node ARM: dts: fix typo on APQ8060 Dragonboard ARM: dts: add SDC2 and SDC4 to the MSM8660 family ARM: dts: msm8974: Hook up adsp-pil's xo clock ARM: dts: qcom: Add msm8974 CoreSight components Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
9ef0f50a23
@ -95,17 +95,17 @@
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function = "sdc1";
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};
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clk {
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pins = "gpio167"; /* SDC5 CLK */
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pins = "gpio167"; /* SDC1 CLK */
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drive-strength = <16>;
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bias-disable;
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};
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cmd {
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pins = "gpio168"; /* SDC5 CMD */
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pins = "gpio168"; /* SDC1 CMD */
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drive-strength = <10>;
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bias-pull-up;
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};
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data {
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/* SDC5 D0 to D7 */
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/* SDC1 D0 to D7 */
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pins = "gpio159", "gpio160", "gpio161", "gpio162",
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"gpio163", "gpio164", "gpio165", "gpio166";
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drive-strength = <10>;
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@ -392,6 +392,21 @@
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cap-mmc-highspeed;
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};
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sdcc2: sdcc@12140000 {
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status = "disabled";
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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reg = <0x12140000 0x8000>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <8>;
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max-frequency = <48000000>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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};
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sdcc3: sdcc@12180000 {
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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@ -408,6 +423,21 @@
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no-1-8-v;
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};
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sdcc4: sdcc@121c0000 {
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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status = "disabled";
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reg = <0x121c0000 0x8000>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <4>;
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max-frequency = <48000000>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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};
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sdcc5: sdcc@12200000 {
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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@ -413,14 +413,6 @@
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dma-controller@f9944000 {
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qcom,controlled-remotely;
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};
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usb-phy@f9a55000 {
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status = "ok";
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};
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usb@f9a55000 {
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status = "ok";
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};
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};
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&spmi_bus {
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@ -2,8 +2,8 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-msm8974.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/reset/qcom,gcc-msm8974.h>
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#include "skeleton.dtsi"
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/ {
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@ -67,7 +67,7 @@
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#size-cells = <0>;
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interrupts = <1 9 0xf04>;
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cpu@0 {
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CPU0: cpu@0 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v2";
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device_type = "cpu";
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@ -78,7 +78,7 @@
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cpu-idle-states = <&CPU_SPC>;
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};
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cpu@1 {
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CPU1: cpu@1 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v2";
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device_type = "cpu";
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@ -89,7 +89,7 @@
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cpu-idle-states = <&CPU_SPC>;
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};
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cpu@2 {
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CPU2: cpu@2 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v2";
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device_type = "cpu";
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@ -100,7 +100,7 @@
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cpu-idle-states = <&CPU_SPC>;
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};
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cpu@3 {
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CPU3: cpu@3 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v2";
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device_type = "cpu";
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@ -250,6 +250,9 @@
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cx-supply = <&pm8841_s2>;
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clocks = <&xo_board>;
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clock-names = "xo";
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memory-region = <&adsp_region>;
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qcom,smem-states = <&adsp_smp2p_out 0>;
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@ -695,42 +698,276 @@
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qcom,ee = <0>;
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};
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usb1_phy: usb-phy@f9a55000 {
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compatible = "qcom,usb-otg-snps";
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etr@fc322000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0xfc322000 0x1000>;
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reg = <0xf9a55000 0x400>;
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interrupts-extended = <&intc 0 134 0>, <&intc 0 140 0>,
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<&spmi_bus 0 0x9 0 0>;
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interrupt-names = "core_irq", "async_irq", "pmic_id_irq";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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vddcx-supply = <&pm8841_s2>;
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v3p3-supply = <&pm8941_l24>;
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v1p8-supply = <&pm8941_l6>;
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dr_mode = "otg";
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qcom,phy-init-sequence = <0x63 0x81 0xfffffff>;
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qcom,otg-control = <1>;
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qcom,phy-num = <0>;
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resets = <&gcc GCC_USB2A_PHY_BCR>, <&gcc GCC_USB_HS_BCR>;
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reset-names = "phy", "link";
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clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>,
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<&gcc GCC_USB_HS_AHB_CLK>;
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clock-names = "phy", "core", "iface";
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status = "disabled";
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port {
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etr_in: endpoint {
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slave-mode;
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remote-endpoint = <&replicator_out0>;
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};
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};
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};
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usb@f9a55000 {
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compatible = "qcom,ci-hdrc";
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reg = <0xf9a55000 0x400>;
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dr_mode = "otg";
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interrupts = <0 134 0>, <0 140 0>;
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interrupt-names = "core_irq", "async_irq";
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usb-phy = <&usb1_phy>;
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tpiu@fc318000 {
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compatible = "arm,coresight-tpiu", "arm,primecell";
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reg = <0xfc318000 0x1000>;
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status = "disabled";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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port {
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tpiu_in: endpoint {
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slave-mode;
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remote-endpoint = <&replicator_out1>;
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};
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};
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};
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replicator@fc31c000 {
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compatible = "qcom,coresight-replicator1x", "arm,primecell";
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reg = <0xfc31c000 0x1000>;
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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replicator_out0: endpoint {
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remote-endpoint = <&etr_in>;
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};
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};
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port@1 {
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reg = <1>;
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replicator_out1: endpoint {
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remote-endpoint = <&tpiu_in>;
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};
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};
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port@2 {
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reg = <0>;
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replicator_in: endpoint {
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slave-mode;
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remote-endpoint = <&etf_out>;
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};
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};
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};
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};
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etf@fc307000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0xfc307000 0x1000>;
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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etf_out: endpoint {
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remote-endpoint = <&replicator_in>;
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};
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};
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port@1 {
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reg = <0>;
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etf_in: endpoint {
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slave-mode;
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remote-endpoint = <&merger_out>;
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};
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};
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};
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};
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funnel@fc31b000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0xfc31b000 0x1000>;
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/*
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* Not described input ports:
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* 0 - connected trought funnel to Audio, Modem and
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* Resource and Power Manager CPU's
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* 2...7 - not-connected
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*/
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port@1 {
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reg = <1>;
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merger_in1: endpoint {
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slave-mode;
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remote-endpoint = <&funnel1_out>;
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};
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};
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port@8 {
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reg = <0>;
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merger_out: endpoint {
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remote-endpoint = <&etf_in>;
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};
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};
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};
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};
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funnel@fc31a000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0xfc31a000 0x1000>;
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/*
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* Not described input ports:
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* 0 - not-connected
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* 1 - connected trought funnel to Multimedia CPU
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* 2 - connected to Wireless CPU
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* 3 - not-connected
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* 4 - not-connected
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* 6 - not-connected
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* 7 - connected to STM
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*/
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port@5 {
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reg = <5>;
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funnel1_in5: endpoint {
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slave-mode;
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remote-endpoint = <&kpss_out>;
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};
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};
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port@8 {
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reg = <0>;
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funnel1_out: endpoint {
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remote-endpoint = <&merger_in1>;
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};
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};
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};
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};
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funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0xfc345000 0x1000>;
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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ports {
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||||
#address-cells = <1>;
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||||
#size-cells = <0>;
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||||
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||||
port@0 {
|
||||
reg = <0>;
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||||
kpss_in0: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&etm0_out>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
kpss_in1: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&etm1_out>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
kpss_in2: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&etm2_out>;
|
||||
};
|
||||
};
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
kpss_in3: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&etm3_out>;
|
||||
};
|
||||
};
|
||||
port@8 {
|
||||
reg = <0>;
|
||||
kpss_out: endpoint {
|
||||
remote-endpoint = <&funnel1_in5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@fc33c000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0xfc33c000 0x1000>;
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
||||
cpu = <&CPU0>;
|
||||
|
||||
port {
|
||||
etm0_out: endpoint {
|
||||
remote-endpoint = <&kpss_in0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@fc33d000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0xfc33d000 0x1000>;
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
||||
cpu = <&CPU1>;
|
||||
|
||||
port {
|
||||
etm1_out: endpoint {
|
||||
remote-endpoint = <&kpss_in1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@fc33e000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0xfc33e000 0x1000>;
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
||||
cpu = <&CPU2>;
|
||||
|
||||
port {
|
||||
etm2_out: endpoint {
|
||||
remote-endpoint = <&kpss_in2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@fc33f000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0xfc33f000 0x1000>;
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
||||
cpu = <&CPU3>;
|
||||
|
||||
port {
|
||||
etm3_out: endpoint {
|
||||
remote-endpoint = <&kpss_in3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -760,6 +997,11 @@
|
||||
compatible = "qcom,rpm-msm8974";
|
||||
qcom,smd-channels = "rpm_requests";
|
||||
|
||||
rpmcc: clock-controller {
|
||||
compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pm8841-regulators {
|
||||
compatible = "qcom,rpm-pm8841-regulators";
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user