drm/radeon: disable pll sharing for DP on DCE4.1
Causes display problems. We had already disabled sharing for non-DP displays. Based on a patch from: Niels Ole Salscheider <niels_ole@salscheider-online.de> bug: https://bugzilla.kernel.org/show_bug.cgi?id=58121 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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@ -1774,6 +1774,20 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
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return ATOM_PPLL1;
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return ATOM_PPLL1;
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DRM_ERROR("unable to allocate a PPLL\n");
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DRM_ERROR("unable to allocate a PPLL\n");
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return ATOM_PPLL_INVALID;
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return ATOM_PPLL_INVALID;
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} else if (ASIC_IS_DCE41(rdev)) {
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/* Don't share PLLs on DCE4.1 chips */
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if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
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if (rdev->clock.dp_extclk)
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/* skip PPLL programming if using ext clock */
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return ATOM_PPLL_INVALID;
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}
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pll_in_use = radeon_get_pll_use_mask(crtc);
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if (!(pll_in_use & (1 << ATOM_PPLL1)))
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return ATOM_PPLL1;
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if (!(pll_in_use & (1 << ATOM_PPLL2)))
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return ATOM_PPLL2;
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DRM_ERROR("unable to allocate a PPLL\n");
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return ATOM_PPLL_INVALID;
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} else if (ASIC_IS_DCE4(rdev)) {
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} else if (ASIC_IS_DCE4(rdev)) {
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/* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
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/* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
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* depending on the asic:
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* depending on the asic:
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@ -1801,7 +1815,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
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if (pll != ATOM_PPLL_INVALID)
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if (pll != ATOM_PPLL_INVALID)
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return pll;
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return pll;
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}
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}
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} else if (!ASIC_IS_DCE41(rdev)) { /* Don't share PLLs on DCE4.1 chips */
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} else {
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/* use the same PPLL for all monitors with the same clock */
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/* use the same PPLL for all monitors with the same clock */
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pll = radeon_get_shared_nondp_ppll(crtc);
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pll = radeon_get_shared_nondp_ppll(crtc);
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if (pll != ATOM_PPLL_INVALID)
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if (pll != ATOM_PPLL_INVALID)
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