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net: dsa: microchip: add property to select internal RMII reference clock

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Microchip KSZ8863/KSZ8873 have the ability to select between internal
and external RMII reference clock. By default, reference clock
needs to be provided via REFCLKI_3 pin. If required, device can be
setup to provide RMII clock internally so that REFCLKI_3 pin can be
left unconnected.
Add a new "microchip,rmii-clk-internal" property which will set
RMII clock reference to internal. If property is not set, reference
clock needs to be provided externally.

While at it, move the ksz8795_cpu_interface_select() to
ksz8_config_cpu_port() to get a cleaner call path for cpu port.

Signed-off-by: Ante Knezic <ante.knezic@helmholz.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ante Knezic 2023-12-05 11:03:39 +01:00 committed by David S. Miller
parent 8e3bfaab2a
commit 9f19a4ebc8
2 changed files with 26 additions and 6 deletions
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29
drivers/net/dsa/microchip/ksz8795.c
View File

@ -1358,6 +1358,9 @@ static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)
{ {
struct ksz_port *p = &dev->ports[port]; struct ksz_port *p = &dev->ports[port];
if (!ksz_is_ksz87xx(dev))
return;
if (!p->interface && dev->compat_interface) { if (!p->interface && dev->compat_interface) {
dev_warn(dev->dev, dev_warn(dev->dev,
"Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
@ -1391,18 +1394,29 @@ void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port)
/* enable 802.1p priority */ /* enable 802.1p priority */
ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true); ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true);
if (cpu_port) { if (cpu_port)
if (!ksz_is_ksz88x3(dev))
ksz8795_cpu_interface_select(dev, port);
member = dsa_user_ports(ds); member = dsa_user_ports(ds);
} else { else
member = BIT(dsa_upstream_port(ds, port)); member = BIT(dsa_upstream_port(ds, port));
}
ksz8_cfg_port_member(dev, port, member); ksz8_cfg_port_member(dev, port, member);
} }
static void ksz88x3_config_rmii_clk(struct ksz_device *dev)
{
struct dsa_port *cpu_dp = dsa_to_port(dev->ds, dev->cpu_port);
bool rmii_clk_internal;
if (!ksz_is_ksz88x3(dev))
return;
rmii_clk_internal = of_property_read_bool(cpu_dp->dn,
"microchip,rmii-clk-internal");
ksz_cfg(dev, KSZ88X3_REG_FVID_AND_HOST_MODE,
KSZ88X3_PORT3_RMII_CLK_INTERNAL, rmii_clk_internal);
}
void ksz8_config_cpu_port(struct dsa_switch *ds) void ksz8_config_cpu_port(struct dsa_switch *ds)
{ {
struct ksz_device *dev = ds->priv; struct ksz_device *dev = ds->priv;
@ -1419,6 +1433,9 @@ void ksz8_config_cpu_port(struct dsa_switch *ds)
ksz8_port_setup(dev, dev->cpu_port, true); ksz8_port_setup(dev, dev->cpu_port, true);
ksz8795_cpu_interface_select(dev, dev->cpu_port);
ksz88x3_config_rmii_clk(dev);
for (i = 0; i < dev->phy_port_cnt; i++) { for (i = 0; i < dev->phy_port_cnt; i++) {
ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED); ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED);
} }

3
drivers/net/dsa/microchip/ksz8795_reg.h
View File

@ -22,6 +22,9 @@
#define KSZ8863_GLOBAL_SOFTWARE_RESET BIT(4) #define KSZ8863_GLOBAL_SOFTWARE_RESET BIT(4)
#define KSZ8863_PCS_RESET BIT(0) #define KSZ8863_PCS_RESET BIT(0)
#define KSZ88X3_REG_FVID_AND_HOST_MODE 0xC6
#define KSZ88X3_PORT3_RMII_CLK_INTERNAL BIT(3)
#define REG_SW_CTRL_0 0x02 #define REG_SW_CTRL_0 0x02
#define SW_NEW_BACKOFF BIT(7) #define SW_NEW_BACKOFF BIT(7)