net: stmmac: Add EST errors into ethtool statistic
Below EST errors are added into ethtool statistic: 1) Constant Gate Control Error (CGCE): The counter "mtl_est_cgce" increases everytime CGCE interrupt is triggered. 2) Head-of-Line Blocking due to Scheduling (HLBS): The counter "mtl_est_hlbs" increases everytime HLBS interrupt is triggered. 3) Head-of-Line Blocking due to Frame Size (HLBF): The counter "mtl_est_hlbf" increases everytime HLBF interrupt is triggered. 4) Base Time Register error (BTRE): The counter "mtl_est_btre" increases everytime BTRE interrupt is triggered but BTRL not reaches maximum value of 15. 5) Base Time Register Error Loop Count (BTRL) reaches maximum value: The counter "mtl_est_btrlm" increases everytime BTRE interrupt is triggered and BTRL value reaches maximum value of 15. Please refer to MTL_EST_STATUS register in DesignWare Cores Ethernet Quality-of-Service Databook for more detail explanation. Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com> Signed-off-by: Voon Weifeng <weifeng.voon@intel.com> Co-developed-by: Mohammad Athari Bin Ismail <mohammad.athari.ismail@intel.com> Signed-off-by: Mohammad Athari Bin Ismail <mohammad.athari.ismail@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -182,6 +182,12 @@ struct stmmac_extra_stats {
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/* TSO */
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unsigned long tx_tso_frames;
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unsigned long tx_tso_nfrags;
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/* EST */
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unsigned long mtl_est_cgce;
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unsigned long mtl_est_hlbs;
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unsigned long mtl_est_hlbf;
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unsigned long mtl_est_btre;
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unsigned long mtl_est_btrlm;
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};
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/* Safety Feature statistics exposed by ethtool */
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@ -608,7 +608,7 @@ int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,
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}
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void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev,
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u32 txqcnt)
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struct stmmac_extra_stats *x, u32 txqcnt)
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{
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u32 status, value, feqn, hbfq, hbfs, btrl;
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u32 txqcnt_mask = (1 << txqcnt) - 1;
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@ -624,12 +624,16 @@ void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev,
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if (status & CGCE) {
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/* Clear Interrupt */
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writel(CGCE, ioaddr + MTL_EST_STATUS);
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x->mtl_est_cgce++;
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}
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if (status & HLBS) {
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value = readl(ioaddr + MTL_EST_SCH_ERR);
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value &= txqcnt_mask;
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x->mtl_est_hlbs++;
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/* Clear Interrupt */
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writel(value, ioaddr + MTL_EST_SCH_ERR);
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@ -649,6 +653,8 @@ void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev,
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hbfq = (value & SZ_CAP_HBFQ_MASK(txqcnt)) >> SZ_CAP_HBFQ_SHIFT;
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hbfs = value & SZ_CAP_HBFS_MASK;
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x->mtl_est_hlbf++;
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/* Clear Interrupt */
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writel(feqn, ioaddr + MTL_EST_FRM_SZ_ERR);
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@ -658,6 +664,11 @@ void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev,
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}
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if (status & BTRE) {
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if ((status & BTRL) == BTRL_MAX)
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x->mtl_est_btrlm++;
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else
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x->mtl_est_btre++;
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btrl = (status & BTRL) >> BTRL_SHIFT;
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if (net_ratelimit())
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@ -142,7 +142,7 @@ int dwmac5_flex_pps_config(void __iomem *ioaddr, int index,
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int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,
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unsigned int ptp_rate);
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void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev,
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u32 txqcnt);
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struct stmmac_extra_stats *x, u32 txqcnt);
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void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,
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bool enable);
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@ -394,7 +394,7 @@ struct stmmac_ops {
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int (*est_configure)(void __iomem *ioaddr, struct stmmac_est *cfg,
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unsigned int ptp_rate);
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void (*est_irq_status)(void __iomem *ioaddr, struct net_device *dev,
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u32 txqcnt);
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struct stmmac_extra_stats *x, u32 txqcnt);
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void (*fpe_configure)(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,
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bool enable);
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};
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@ -158,6 +158,12 @@ static const struct stmmac_stats stmmac_gstrings_stats[] = {
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/* TSO */
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STMMAC_STAT(tx_tso_frames),
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STMMAC_STAT(tx_tso_nfrags),
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/* EST */
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STMMAC_STAT(mtl_est_cgce),
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STMMAC_STAT(mtl_est_hlbs),
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STMMAC_STAT(mtl_est_hlbf),
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STMMAC_STAT(mtl_est_btre),
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STMMAC_STAT(mtl_est_btrlm),
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};
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#define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats)
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@ -4315,7 +4315,8 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
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return IRQ_HANDLED;
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if (priv->dma_cap.estsel)
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stmmac_est_irq_status(priv, priv->ioaddr, priv->dev, tx_cnt);
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stmmac_est_irq_status(priv, priv->ioaddr, priv->dev,
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&priv->xstats, tx_cnt);
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/* To handle GMAC own interrupts */
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if ((priv->plat->has_gmac) || xmac) {
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