amd-drm-fixes-6.7-2023-12-06:
amdgpu: - Disable MCBP on gfx9 - DC vbios fix - eDP fix - dml2 UBSAN fix - SMU 14 fix - RAS fixes - dml KASAN/KCSAN fix - PSP 13 fix - Clockgating fixes - Suspend fix -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQgO5Idg2tXNTSZAr293/aFa7yZ2AUCZXDwjQAKCRC93/aFa7yZ 2KweAPoCF41L1O8ypNmop5LIkmen9lAwpJLpc2N0c2iZD/iMwgEA2F87hiz8juW5 +UTpM9XxlrjJ3QOz5PHAIGXGkNcnPQE= =mDjj -----END PGP SIGNATURE----- Merge tag 'amd-drm-fixes-6.7-2023-12-06' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes amd-drm-fixes-6.7-2023-12-06: amdgpu: - Disable MCBP on gfx9 - DC vbios fix - eDP fix - dml2 UBSAN fix - SMU 14 fix - RAS fixes - dml KASAN/KCSAN fix - PSP 13 fix - Clockgating fixes - Suspend fix Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231206221102.4995-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie
commit
9f3e1c5919
@ -3791,10 +3791,6 @@ static void amdgpu_device_set_mcbp(struct amdgpu_device *adev)
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adev->gfx.mcbp = true;
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else if (amdgpu_mcbp == 0)
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adev->gfx.mcbp = false;
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else if ((amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 0, 0)) &&
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(amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 0, 0)) &&
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adev->gfx.num_gfx_rings)
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adev->gfx.mcbp = true;
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if (amdgpu_sriov_vf(adev))
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adev->gfx.mcbp = true;
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@ -4531,6 +4527,8 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
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if (r)
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return r;
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amdgpu_ttm_set_buffer_funcs_status(adev, false);
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amdgpu_fence_driver_hw_fini(adev);
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amdgpu_device_ip_suspend_phase2(adev);
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@ -46,6 +46,8 @@
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#define MCA_REG__STATUS__ERRORCODEEXT(x) MCA_REG_FIELD(x, 21, 16)
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#define MCA_REG__STATUS__ERRORCODE(x) MCA_REG_FIELD(x, 15, 0)
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#define MCA_REG__SYND__ERRORINFORMATION(x) MCA_REG_FIELD(x, 17, 0)
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enum amdgpu_mca_ip {
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AMDGPU_MCA_IP_UNKNOW = -1,
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AMDGPU_MCA_IP_PSP = 0,
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@ -28,6 +28,7 @@
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#include <linux/reboot.h>
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#include <linux/syscalls.h>
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#include <linux/pm_runtime.h>
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#include <linux/list_sort.h>
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#include "amdgpu.h"
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#include "amdgpu_ras.h"
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@ -3665,6 +3666,21 @@ static struct ras_err_node *amdgpu_ras_error_node_new(void)
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return err_node;
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}
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static int ras_err_info_cmp(void *priv, const struct list_head *a, const struct list_head *b)
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{
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struct ras_err_node *nodea = container_of(a, struct ras_err_node, node);
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struct ras_err_node *nodeb = container_of(b, struct ras_err_node, node);
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struct amdgpu_smuio_mcm_config_info *infoa = &nodea->err_info.mcm_info;
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struct amdgpu_smuio_mcm_config_info *infob = &nodeb->err_info.mcm_info;
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if (unlikely(infoa->socket_id != infob->socket_id))
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return infoa->socket_id - infob->socket_id;
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else
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return infoa->die_id - infob->die_id;
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return 0;
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}
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static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_data,
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struct amdgpu_smuio_mcm_config_info *mcm_info)
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{
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@ -3682,6 +3698,7 @@ static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_d
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err_data->err_list_count++;
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list_add_tail(&err_node->node, &err_data->err_node_list);
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list_sort(NULL, &err_data->err_node_list, ras_err_info_cmp);
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return &err_node->err_info;
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}
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@ -129,6 +129,11 @@ static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,
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{
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int data;
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if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2)) {
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/* Default enabled */
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*flags |= AMD_CG_SUPPORT_HDP_MGCG;
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return;
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}
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/* AMD_CG_SUPPORT_HDP_LS */
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data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
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if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
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@ -60,7 +60,7 @@ MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");
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#define GFX_CMD_USB_PD_USE_LFB 0x480
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/* Retry times for vmbx ready wait */
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#define PSP_VMBX_POLLING_LIMIT 20000
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#define PSP_VMBX_POLLING_LIMIT 3000
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/* VBIOS gfl defines */
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#define MBOX_READY_MASK 0x80000000
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@ -161,14 +161,18 @@ static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp)
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static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
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{
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struct amdgpu_device *adev = psp->adev;
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int retry_loop, ret;
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int retry_loop, retry_cnt, ret;
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retry_cnt =
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(amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) ?
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PSP_VMBX_POLLING_LIMIT :
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10;
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/* Wait for bootloader to signify that it is ready having bit 31 of
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* C2PMSG_35 set to 1. All other bits are expected to be cleared.
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* If there is an error in processing command, bits[7:0] will be set.
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* This is applicable for PSP v13.0.6 and newer.
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*/
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for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) {
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for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) {
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ret = psp_wait_for(
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psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
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0x80000000, 0xffffffff, false);
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@ -821,7 +825,7 @@ static int psp_v13_0_query_boot_status(struct psp_context *psp)
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if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))
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return 0;
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if (RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_59) < 0x00a10007)
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if (RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_59) < 0x00a10109)
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return 0;
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for_each_inst(i, inst_mask) {
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@ -1423,11 +1423,14 @@ static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
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if (amdgpu_sriov_vf(adev))
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*flags = 0;
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adev->nbio.funcs->get_clockgating_state(adev, flags);
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if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state)
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adev->nbio.funcs->get_clockgating_state(adev, flags);
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adev->hdp.funcs->get_clock_gating_state(adev, flags);
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if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state)
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adev->hdp.funcs->get_clock_gating_state(adev, flags);
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if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) {
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if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) &&
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(amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))) {
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/* AMD_CG_SUPPORT_DRM_MGCG */
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data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
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if (!(data & 0x01000000))
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@ -1440,9 +1443,11 @@ static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
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}
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/* AMD_CG_SUPPORT_ROM_MGCG */
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adev->smuio.funcs->get_clock_gating_state(adev, flags);
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if (adev->smuio.funcs && adev->smuio.funcs->get_clock_gating_state)
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adev->smuio.funcs->get_clock_gating_state(adev, flags);
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adev->df.funcs->get_clockgating_state(adev, flags);
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if (adev->df.funcs && adev->df.funcs->get_clockgating_state)
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adev->df.funcs->get_clockgating_state(adev, flags);
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}
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static int soc15_common_set_powergating_state(void *handle,
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@ -63,6 +63,12 @@ static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps)
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DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id);
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edid_caps->panel_patch.disable_fams = true;
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break;
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/* Workaround for some monitors that do not clear DPCD 0x317 if FreeSync is unsupported */
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case drm_edid_encode_panel_id('A', 'U', 'O', 0xA7AB):
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case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B):
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DRM_DEBUG_DRIVER("Clearing DPCD 0x317 on monitor with panel id %X\n", panel_id);
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edid_caps->panel_patch.remove_sink_ext_caps = true;
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break;
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default:
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return;
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}
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@ -2386,7 +2386,13 @@ static enum bp_result get_vram_info_v30(
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return BP_RESULT_BADBIOSTABLE;
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info->num_chans = info_v30->channel_num;
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info->dram_channel_width_bytes = (1 << info_v30->channel_width) / 8;
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/* As suggested by VBIOS we should always use
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* dram_channel_width_bytes = 2 when using VRAM
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* table version 3.0. This is because the channel_width
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* param in the VRAM info table is changed in 7000 series and
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* no longer represents the memory channel width.
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*/
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info->dram_channel_width_bytes = 2;
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return result;
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}
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@ -61,8 +61,12 @@ endif
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endif
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ifneq ($(CONFIG_FRAME_WARN),0)
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ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)
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frame_warn_flag := -Wframe-larger-than=3072
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else
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frame_warn_flag := -Wframe-larger-than=2048
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endif
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endif
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CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
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@ -9447,12 +9447,12 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc
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// Output
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CalculateWatermarks_params->Watermark = &s->dummy_watermark; // Watermarks *Watermark
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CalculateWatermarks_params->DRAMClockChangeSupport = &mode_lib->ms.support.DRAMClockChangeSupport[j];
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CalculateWatermarks_params->DRAMClockChangeSupport = &mode_lib->ms.support.DRAMClockChangeSupport[0];
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CalculateWatermarks_params->MaxActiveDRAMClockChangeLatencySupported = &s->dummy_single_array[0][0]; // dml_float_t *MaxActiveDRAMClockChangeLatencySupported[]
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CalculateWatermarks_params->SubViewportLinesNeededInMALL = &mode_lib->ms.SubViewportLinesNeededInMALL[j]; // dml_uint_t SubViewportLinesNeededInMALL[]
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CalculateWatermarks_params->FCLKChangeSupport = &mode_lib->ms.support.FCLKChangeSupport[j];
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CalculateWatermarks_params->FCLKChangeSupport = &mode_lib->ms.support.FCLKChangeSupport[0];
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CalculateWatermarks_params->MaxActiveFCLKChangeLatencySupported = &s->dummy_single[0]; // dml_float_t *MaxActiveFCLKChangeLatencySupported
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CalculateWatermarks_params->USRRetrainingSupport = &mode_lib->ms.support.USRRetrainingSupport[j];
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CalculateWatermarks_params->USRRetrainingSupport = &mode_lib->ms.support.USRRetrainingSupport[0];
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CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
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&mode_lib->scratch,
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@ -1085,6 +1085,10 @@ struct gpu_metrics_v3_0 {
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uint16_t average_dram_reads;
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/* time filtered DRAM write bandwidth [MB/sec] */
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uint16_t average_dram_writes;
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/* time filtered IPU read bandwidth [MB/sec] */
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uint16_t average_ipu_reads;
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/* time filtered IPU write bandwidth [MB/sec] */
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uint16_t average_ipu_writes;
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/* Driver attached timestamp (in ns) */
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uint64_t system_clock_counter;
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@ -1104,6 +1108,8 @@ struct gpu_metrics_v3_0 {
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uint32_t average_all_core_power;
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/* calculated core power [mW] */
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uint16_t average_core_power[16];
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/* time filtered total system power [mW] */
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uint16_t average_sys_power;
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/* maximum IRM defined STAPM power limit [mW] */
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uint16_t stapm_power_limit;
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/* time filtered STAPM power limit [mW] */
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@ -1116,6 +1122,8 @@ struct gpu_metrics_v3_0 {
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uint16_t average_ipuclk_frequency;
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uint16_t average_fclk_frequency;
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uint16_t average_vclk_frequency;
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uint16_t average_uclk_frequency;
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uint16_t average_mpipu_frequency;
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/* Current clocks */
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/* target core frequency [MHz] */
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@ -1125,6 +1133,15 @@ struct gpu_metrics_v3_0 {
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/* GFXCLK frequency limit enforced on GFX [MHz] */
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uint16_t current_gfx_maxfreq;
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/* Throttle Residency (ASIC dependent) */
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uint32_t throttle_residency_prochot;
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uint32_t throttle_residency_spl;
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uint32_t throttle_residency_fppt;
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uint32_t throttle_residency_sppt;
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uint32_t throttle_residency_thm_core;
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uint32_t throttle_residency_thm_gfx;
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uint32_t throttle_residency_thm_soc;
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/* Metrics table alpha filter time constant [us] */
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uint32_t time_filter_alphavalue;
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};
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@ -1408,6 +1408,16 @@ typedef enum {
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METRICS_PCIE_WIDTH,
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METRICS_CURR_FANPWM,
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METRICS_CURR_SOCKETPOWER,
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METRICS_AVERAGE_VPECLK,
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METRICS_AVERAGE_IPUCLK,
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METRICS_AVERAGE_MPIPUCLK,
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METRICS_THROTTLER_RESIDENCY_PROCHOT,
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METRICS_THROTTLER_RESIDENCY_SPL,
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METRICS_THROTTLER_RESIDENCY_FPPT,
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METRICS_THROTTLER_RESIDENCY_SPPT,
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METRICS_THROTTLER_RESIDENCY_THM_CORE,
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METRICS_THROTTLER_RESIDENCY_THM_GFX,
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METRICS_THROTTLER_RESIDENCY_THM_SOC,
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} MetricsMember_t;
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enum smu_cmn2asic_mapping_type {
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@ -27,7 +27,7 @@
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// *** IMPORTANT ***
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// SMU TEAM: Always increment the interface version if
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// any structure is changed in this file
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#define PMFW_DRIVER_IF_VERSION 6
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#define PMFW_DRIVER_IF_VERSION 7
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typedef struct {
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int32_t value;
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@ -150,37 +150,50 @@ typedef struct {
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} DpmClocks_t;
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typedef struct {
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uint16_t CoreFrequency[16]; //Target core frequency [MHz]
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uint16_t CorePower[16]; //CAC calculated core power [mW]
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uint16_t CoreTemperature[16]; //TSEN measured core temperature [centi-C]
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uint16_t GfxTemperature; //TSEN measured GFX temperature [centi-C]
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uint16_t SocTemperature; //TSEN measured SOC temperature [centi-C]
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uint16_t StapmOpnLimit; //Maximum IRM defined STAPM power limit [mW]
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uint16_t StapmCurrentLimit; //Time filtered STAPM power limit [mW]
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uint16_t InfrastructureCpuMaxFreq; //CCLK frequency limit enforced on classic cores [MHz]
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uint16_t InfrastructureGfxMaxFreq; //GFXCLK frequency limit enforced on GFX [MHz]
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uint16_t SkinTemp; //Maximum skin temperature reported by APU and HS2 chassis sensors [centi-C]
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uint16_t GfxclkFrequency; //Time filtered target GFXCLK frequency [MHz]
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uint16_t FclkFrequency; //Time filtered target FCLK frequency [MHz]
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uint16_t GfxActivity; //Time filtered GFX busy % [0-100]
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uint16_t SocclkFrequency; //Time filtered target SOCCLK frequency [MHz]
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uint16_t VclkFrequency; //Time filtered target VCLK frequency [MHz]
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uint16_t VcnActivity; //Time filtered VCN busy % [0-100]
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uint16_t VpeclkFrequency; //Time filtered target VPECLK frequency [MHz]
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uint16_t IpuclkFrequency; //Time filtered target IPUCLK frequency [MHz]
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uint16_t IpuBusy[8]; //Time filtered IPU per-column busy % [0-100]
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uint16_t DRAMReads; //Time filtered DRAM read bandwidth [MB/sec]
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uint16_t DRAMWrites; //Time filtered DRAM write bandwidth [MB/sec]
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uint16_t CoreC0Residency[16]; //Time filtered per-core C0 residency % [0-100]
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uint16_t IpuPower; //Time filtered IPU power [mW]
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uint32_t ApuPower; //Time filtered APU power [mW]
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uint32_t GfxPower; //Time filtered GFX power [mW]
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uint32_t dGpuPower; //Time filtered dGPU power [mW]
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uint32_t SocketPower; //Time filtered power used for PPT/STAPM [APU+dGPU] [mW]
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uint32_t AllCorePower; //Time filtered sum of core power across all cores in the socket [mW]
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uint32_t FilterAlphaValue; //Metrics table alpha filter time constant [us]
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uint32_t MetricsCounter; //Counter that is incremented on every metrics table update [PM_TIMER cycles]
|
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uint32_t spare[16];
|
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uint16_t CoreFrequency[16]; //Target core frequency [MHz]
|
||||
uint16_t CorePower[16]; //CAC calculated core power [mW]
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uint16_t CoreTemperature[16]; //TSEN measured core temperature [centi-C]
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uint16_t GfxTemperature; //TSEN measured GFX temperature [centi-C]
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uint16_t SocTemperature; //TSEN measured SOC temperature [centi-C]
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uint16_t StapmOpnLimit; //Maximum IRM defined STAPM power limit [mW]
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uint16_t StapmCurrentLimit; //Time filtered STAPM power limit [mW]
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uint16_t InfrastructureCpuMaxFreq; //CCLK frequency limit enforced on classic cores [MHz]
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uint16_t InfrastructureGfxMaxFreq; //GFXCLK frequency limit enforced on GFX [MHz]
|
||||
uint16_t SkinTemp; //Maximum skin temperature reported by APU and HS2 chassis sensors [centi-C]
|
||||
uint16_t GfxclkFrequency; //Time filtered target GFXCLK frequency [MHz]
|
||||
uint16_t FclkFrequency; //Time filtered target FCLK frequency [MHz]
|
||||
uint16_t GfxActivity; //Time filtered GFX busy % [0-100]
|
||||
uint16_t SocclkFrequency; //Time filtered target SOCCLK frequency [MHz]
|
||||
uint16_t VclkFrequency; //Time filtered target VCLK frequency [MHz]
|
||||
uint16_t VcnActivity; //Time filtered VCN busy % [0-100]
|
||||
uint16_t VpeclkFrequency; //Time filtered target VPECLK frequency [MHz]
|
||||
uint16_t IpuclkFrequency; //Time filtered target IPUCLK frequency [MHz]
|
||||
uint16_t IpuBusy[8]; //Time filtered IPU per-column busy % [0-100]
|
||||
uint16_t DRAMReads; //Time filtered DRAM read bandwidth [MB/sec]
|
||||
uint16_t DRAMWrites; //Time filtered DRAM write bandwidth [MB/sec]
|
||||
uint16_t CoreC0Residency[16]; //Time filtered per-core C0 residency % [0-100]
|
||||
uint16_t IpuPower; //Time filtered IPU power [mW]
|
||||
uint32_t ApuPower; //Time filtered APU power [mW]
|
||||
uint32_t GfxPower; //Time filtered GFX power [mW]
|
||||
uint32_t dGpuPower; //Time filtered dGPU power [mW]
|
||||
uint32_t SocketPower; //Time filtered power used for PPT/STAPM [APU+dGPU] [mW]
|
||||
uint32_t AllCorePower; //Time filtered sum of core power across all cores in the socket [mW]
|
||||
uint32_t FilterAlphaValue; //Metrics table alpha filter time constant [us]
|
||||
uint32_t MetricsCounter; //Counter that is incremented on every metrics table update [PM_TIMER cycles]
|
||||
uint16_t MemclkFrequency; //Time filtered target MEMCLK frequency [MHz]
|
||||
uint16_t MpipuclkFrequency; //Time filtered target MPIPUCLK frequency [MHz]
|
||||
uint16_t IpuReads; //Time filtered IPU read bandwidth [MB/sec]
|
||||
uint16_t IpuWrites; //Time filtered IPU write bandwidth [MB/sec]
|
||||
uint32_t ThrottleResidency_PROCHOT; //Counter that is incremented on every metrics table update when PROCHOT was engaged [PM_TIMER cycles]
|
||||
uint32_t ThrottleResidency_SPL; //Counter that is incremented on every metrics table update when SPL was engaged [PM_TIMER cycles]
|
||||
uint32_t ThrottleResidency_FPPT; //Counter that is incremented on every metrics table update when fast PPT was engaged [PM_TIMER cycles]
|
||||
uint32_t ThrottleResidency_SPPT; //Counter that is incremented on every metrics table update when slow PPT was engaged [PM_TIMER cycles]
|
||||
uint32_t ThrottleResidency_THM_CORE; //Counter that is incremented on every metrics table update when CORE thermal throttling was engaged [PM_TIMER cycles]
|
||||
uint32_t ThrottleResidency_THM_GFX; //Counter that is incremented on every metrics table update when GFX thermal throttling was engaged [PM_TIMER cycles]
|
||||
uint32_t ThrottleResidency_THM_SOC; //Counter that is incremented on every metrics table update when SOC thermal throttling was engaged [PM_TIMER cycles]
|
||||
uint16_t Psys; //Time filtered Psys power [mW]
|
||||
uint16_t spare1;
|
||||
uint32_t spare[6];
|
||||
} SmuMetrics_t;
|
||||
|
||||
//ISP tile definitions
|
||||
|
||||
@ -2593,13 +2593,20 @@ static bool mca_gfx_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct
|
||||
static bool mca_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
|
||||
enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
|
||||
{
|
||||
struct smu_context *smu = adev->powerplay.pp_handle;
|
||||
uint32_t errcode, instlo;
|
||||
|
||||
instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
|
||||
if (instlo != 0x03b30400)
|
||||
return false;
|
||||
|
||||
errcode = REG_GET_FIELD(entry->regs[MCA_REG_IDX_STATUS], MCMP1_STATUST0, ErrorCode);
|
||||
if (!(adev->flags & AMD_IS_APU) && smu->smc_fw_version >= 0x00555600) {
|
||||
errcode = MCA_REG__SYND__ERRORINFORMATION(entry->regs[MCA_REG_IDX_SYND]);
|
||||
errcode &= 0xff;
|
||||
} else {
|
||||
errcode = REG_GET_FIELD(entry->regs[MCA_REG_IDX_STATUS], MCMP1_STATUST0, ErrorCode);
|
||||
}
|
||||
|
||||
return mca_smu_check_error_code(adev, mca_ras, errcode);
|
||||
}
|
||||
|
||||
|
||||
@ -246,11 +246,20 @@ static int smu_v14_0_0_get_smu_metrics_data(struct smu_context *smu,
|
||||
*value = 0;
|
||||
break;
|
||||
case METRICS_AVERAGE_UCLK:
|
||||
*value = 0;
|
||||
*value = metrics->MemclkFrequency;
|
||||
break;
|
||||
case METRICS_AVERAGE_FCLK:
|
||||
*value = metrics->FclkFrequency;
|
||||
break;
|
||||
case METRICS_AVERAGE_VPECLK:
|
||||
*value = metrics->VpeclkFrequency;
|
||||
break;
|
||||
case METRICS_AVERAGE_IPUCLK:
|
||||
*value = metrics->IpuclkFrequency;
|
||||
break;
|
||||
case METRICS_AVERAGE_MPIPUCLK:
|
||||
*value = metrics->MpipuclkFrequency;
|
||||
break;
|
||||
case METRICS_AVERAGE_GFXACTIVITY:
|
||||
*value = metrics->GfxActivity / 100;
|
||||
break;
|
||||
@ -270,8 +279,26 @@ static int smu_v14_0_0_get_smu_metrics_data(struct smu_context *smu,
|
||||
*value = metrics->SocTemperature / 100 *
|
||||
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
|
||||
break;
|
||||
case METRICS_THROTTLER_STATUS:
|
||||
*value = 0;
|
||||
case METRICS_THROTTLER_RESIDENCY_PROCHOT:
|
||||
*value = metrics->ThrottleResidency_PROCHOT;
|
||||
break;
|
||||
case METRICS_THROTTLER_RESIDENCY_SPL:
|
||||
*value = metrics->ThrottleResidency_SPL;
|
||||
break;
|
||||
case METRICS_THROTTLER_RESIDENCY_FPPT:
|
||||
*value = metrics->ThrottleResidency_FPPT;
|
||||
break;
|
||||
case METRICS_THROTTLER_RESIDENCY_SPPT:
|
||||
*value = metrics->ThrottleResidency_SPPT;
|
||||
break;
|
||||
case METRICS_THROTTLER_RESIDENCY_THM_CORE:
|
||||
*value = metrics->ThrottleResidency_THM_CORE;
|
||||
break;
|
||||
case METRICS_THROTTLER_RESIDENCY_THM_GFX:
|
||||
*value = metrics->ThrottleResidency_THM_GFX;
|
||||
break;
|
||||
case METRICS_THROTTLER_RESIDENCY_THM_SOC:
|
||||
*value = metrics->ThrottleResidency_THM_SOC;
|
||||
break;
|
||||
case METRICS_VOLTAGE_VDDGFX:
|
||||
*value = 0;
|
||||
@ -498,6 +525,8 @@ static ssize_t smu_v14_0_0_get_gpu_metrics(struct smu_context *smu,
|
||||
sizeof(uint16_t) * 16);
|
||||
gpu_metrics->average_dram_reads = metrics.DRAMReads;
|
||||
gpu_metrics->average_dram_writes = metrics.DRAMWrites;
|
||||
gpu_metrics->average_ipu_reads = metrics.IpuReads;
|
||||
gpu_metrics->average_ipu_writes = metrics.IpuWrites;
|
||||
|
||||
gpu_metrics->average_socket_power = metrics.SocketPower;
|
||||
gpu_metrics->average_ipu_power = metrics.IpuPower;
|
||||
@ -505,6 +534,7 @@ static ssize_t smu_v14_0_0_get_gpu_metrics(struct smu_context *smu,
|
||||
gpu_metrics->average_gfx_power = metrics.GfxPower;
|
||||
gpu_metrics->average_dgpu_power = metrics.dGpuPower;
|
||||
gpu_metrics->average_all_core_power = metrics.AllCorePower;
|
||||
gpu_metrics->average_sys_power = metrics.Psys;
|
||||
memcpy(&gpu_metrics->average_core_power[0],
|
||||
&metrics.CorePower[0],
|
||||
sizeof(uint16_t) * 16);
|
||||
@ -515,6 +545,8 @@ static ssize_t smu_v14_0_0_get_gpu_metrics(struct smu_context *smu,
|
||||
gpu_metrics->average_fclk_frequency = metrics.FclkFrequency;
|
||||
gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
|
||||
gpu_metrics->average_ipuclk_frequency = metrics.IpuclkFrequency;
|
||||
gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
|
||||
gpu_metrics->average_mpipu_frequency = metrics.MpipuclkFrequency;
|
||||
|
||||
memcpy(&gpu_metrics->current_coreclk[0],
|
||||
&metrics.CoreFrequency[0],
|
||||
@ -522,6 +554,14 @@ static ssize_t smu_v14_0_0_get_gpu_metrics(struct smu_context *smu,
|
||||
gpu_metrics->current_core_maxfreq = metrics.InfrastructureCpuMaxFreq;
|
||||
gpu_metrics->current_gfx_maxfreq = metrics.InfrastructureGfxMaxFreq;
|
||||
|
||||
gpu_metrics->throttle_residency_prochot = metrics.ThrottleResidency_PROCHOT;
|
||||
gpu_metrics->throttle_residency_spl = metrics.ThrottleResidency_SPL;
|
||||
gpu_metrics->throttle_residency_fppt = metrics.ThrottleResidency_FPPT;
|
||||
gpu_metrics->throttle_residency_sppt = metrics.ThrottleResidency_SPPT;
|
||||
gpu_metrics->throttle_residency_thm_core = metrics.ThrottleResidency_THM_CORE;
|
||||
gpu_metrics->throttle_residency_thm_gfx = metrics.ThrottleResidency_THM_GFX;
|
||||
gpu_metrics->throttle_residency_thm_soc = metrics.ThrottleResidency_THM_SOC;
|
||||
|
||||
gpu_metrics->time_filter_alphavalue = metrics.FilterAlphaValue;
|
||||
gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user