drm/amd/display: Add 16 lines margin for SubVP
[Description] SUBVP_START_LINE must be aligned to 2 swaths, so add 16 lines of margin so the start line can be adjusted by up to 16 lines for alignment purposes in FW. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -213,6 +213,7 @@ struct dc_caps {
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uint32_t cache_num_ways;
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uint16_t subvp_fw_processing_delay_us;
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uint16_t subvp_prefetch_end_to_mall_start_us;
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uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height
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uint16_t subvp_pstate_allow_width_us;
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uint16_t subvp_vertical_int_margin_us;
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bool seamless_odm;
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@ -275,8 +275,7 @@ void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst)
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union dmub_rb_cmd cmd = { 0 };
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cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
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// TODO: Uncomment once FW headers are promoted
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//cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER;
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cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER;
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cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
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cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);
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@ -612,6 +611,7 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc,
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main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable;
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pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable;
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pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->pipe_idx;
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pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param;
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// Prefetch lines is equal to VACTIVE + BP + VSYNC
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pipe_data->pipe_config.subvp_data.prefetch_lines =
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@ -281,7 +281,7 @@ static struct timing_generator_funcs dcn32_tg_funcs = {
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.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
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.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
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.enable_optc_clock = optc1_enable_optc_clock,
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.set_drr = optc31_set_drr, // TODO: Update to optc32_set_drr once FW headers are promoted
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.set_drr = optc32_set_drr,
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.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
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.set_vtotal_min_max = optc3_set_vtotal_min_max,
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.set_static_screen_control = optc1_set_static_screen_control,
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@ -2051,6 +2051,7 @@ static bool dcn32_resource_construct(
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dc->caps.max_cab_allocation_bytes = 67108864; // 64MB = 1024 * 1024 * 64
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dc->caps.subvp_fw_processing_delay_us = 15;
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dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
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dc->caps.subvp_swath_height_margin_lines = 16;
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dc->caps.subvp_pstate_allow_width_us = 20;
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dc->caps.subvp_vertical_int_margin_us = 30;
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@ -1662,6 +1662,7 @@ static bool dcn321_resource_construct(
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dc->caps.max_cab_allocation_bytes = 33554432; // 32MB = 1024 * 1024 * 32
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dc->caps.subvp_fw_processing_delay_us = 15;
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dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
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dc->caps.subvp_swath_height_margin_lines = 16;
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dc->caps.subvp_pstate_allow_width_us = 20;
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dc->caps.max_slave_planes = 1;
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@ -473,8 +473,11 @@ void dcn32_set_phantom_stream_timing(struct dc *dc,
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// DML calculation for MALL region doesn't take into account FW delay
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// and required pstate allow width for multi-display cases
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/* Add 16 lines margin to the MALL REGION because SUB_VP_START_LINE must be aligned
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* to 2 swaths (i.e. 16 lines)
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*/
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phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) +
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pstate_width_fw_delay_lines;
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pstate_width_fw_delay_lines + dc->caps.subvp_swath_height_margin_lines;
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// For backporch of phantom pipe, use vstartup of the main pipe
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phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
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