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dt-bindings: mtd: intel: lgm-nand: Fix maximum chip select value

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The Intel LGM NAND IP only supports two chip selects: There's only two
CS and ADDR_SEL register sets. Fix the maximum allowed chip select value
according to the dt-bindings.

Fixes: 2f9cea8eae44f5 ("dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC")
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20220702231227.1579176-3-martin.blumenstingl@googlemail.com
This commit is contained in:
Martin Blumenstingl 2022-07-03 01:12:21 +02:00 committed by Miquel Raynal
parent c6d7ce0a7e
commit 9fac2a193e
1 changed files with 1 additions and 1 deletions
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2
Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml
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@ -51,7 +51,7 @@ patternProperties:
properties:
reg:
minimum: 0
maximum: 7
maximum: 1
nand-ecc-mode: true