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MIPS: R2: Fix problem with code that incorrectly modifies ebase.

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Commit 566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e had a change that
incorrectly modified ebase. This backs out the lines that modified
ebase.
In addition, the ebase exception vector is now allocated with correct
alignment and the ebase register updated according to the architecture
specification.

Based on original patch by David VomLehn <dvomlehn@cisco.com>.

Signed-off-by: David VomLehn <dvomlehn@cisco.com>
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Chris Dearman 2009-03-20 15:33:55 -07:00 committed by Ralf Baechle
parent 89e18eb331
commit 9fb4c2b9e0
1 changed files with 7 additions and 5 deletions
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12
arch/mips/kernel/traps.c
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@ -1520,7 +1520,9 @@ void __cpuinit per_cpu_trap_init(void)
#endif /* CONFIG_MIPS_MT_SMTC */ #endif /* CONFIG_MIPS_MT_SMTC */
if (cpu_has_veic || cpu_has_vint) { if (cpu_has_veic || cpu_has_vint) {
unsigned long sr = set_c0_status(ST0_BEV);
write_c0_ebase(ebase); write_c0_ebase(ebase);
write_c0_status(sr);
/* Setting vector spacing enables EI/VI mode */ /* Setting vector spacing enables EI/VI mode */
change_c0_intctl(0x3e0, VECTORSPACING); change_c0_intctl(0x3e0, VECTORSPACING);
} }
@ -1602,8 +1604,6 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
#ifdef CONFIG_64BIT #ifdef CONFIG_64BIT
unsigned long uncached_ebase = TO_UNCAC(ebase); unsigned long uncached_ebase = TO_UNCAC(ebase);
#endif #endif
if (cpu_has_mips_r2)
uncached_ebase += (read_c0_ebase() & 0x3ffff000);
if (!addr) if (!addr)
panic(panic_null_cerr); panic(panic_null_cerr);
@ -1635,9 +1635,11 @@ void __init trap_init(void)
return; /* Already done */ return; /* Already done */
#endif #endif
if (cpu_has_veic || cpu_has_vint) if (cpu_has_veic || cpu_has_vint) {
ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); unsigned long size = 0x200 + VECTORSPACING*64;
else { ebase = (unsigned long)
__alloc_bootmem(size, 1 << fls(size), 0);
} else {
ebase = CAC_BASE; ebase = CAC_BASE;
if (cpu_has_mips_r2) if (cpu_has_mips_r2)
ebase += (read_c0_ebase() & 0x3ffff000); ebase += (read_c0_ebase() & 0x3ffff000);