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clk: renesas: rzg2l: Fix reset status function

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[ Upstream commit 02c96ed9e4cd1f47bfcd10296fec6b0b69d6b3c6 ]

As per RZ/G2L HW(Rev.1.10) manual, reset monitor register value 0 means
reset signal is not applied (deassert state) and 1 means reset signal
is applied (assert state).

reset_control_status() expects a positive value if the reset line is
asserted. But rzg2l_cpg_status function returns zero for asserted
state.

This patch fixes the issue by adding double inverted logic, so that
reset_control_status returns a positive value if the reset line is
asserted.

Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220531071657.104121-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Biju Das 2022-05-31 08:16:57 +01:00 committed by Greg Kroah-Hartman
parent f1e715d4a4
commit a04c62f42a
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/renesas/rzg2l-cpg.c
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@ -1180,7 +1180,7 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
s8 monbit = info->resets[id].monbit;
if (info->has_clk_mon_regs) {
return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
return !!(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
} else if (monbit >= 0) {
u32 monbitmask = BIT(monbit);