ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
ETZPC is a firewall controller. Put all peripherals filtered by the ETZPC as ETZPC subnodes and keep the "simple-bus" compatible for backward compatibility. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
This commit is contained in:
Gatien Chevallier
committed by
Alexandre Torgue
Alexandre Torgue
parent
ad4263523f
commit
a06b9560eb
@ -745,6 +745,153 @@
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dma-channels = <16>;
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};
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rcc: rcc@50000000 {
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compatible = "st,stm32mp13-rcc", "syscon";
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reg = <0x50000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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clock-names = "hse", "hsi", "csi", "lse", "lsi";
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clocks = <&scmi_clk CK_SCMI_HSE>,
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<&scmi_clk CK_SCMI_HSI>,
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<&scmi_clk CK_SCMI_CSI>,
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<&scmi_clk CK_SCMI_LSE>,
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<&scmi_clk CK_SCMI_LSI>;
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};
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exti: interrupt-controller@5000d000 {
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compatible = "st,stm32mp13-exti", "syscon";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x5000d000 0x400>;
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};
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syscfg: syscon@50020000 {
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compatible = "st,stm32mp157-syscfg", "syscon";
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reg = <0x50020000 0x400>;
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clocks = <&rcc SYSCFG>;
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};
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lptimer4: timer@50023000 {
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compatible = "st,stm32-lptimer";
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reg = <0x50023000 0x400>;
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interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc LPTIM4_K>;
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clock-names = "mux";
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wakeup-source;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm-lp";
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#pwm-cells = <3>;
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status = "disabled";
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};
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timer {
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compatible = "st,stm32-lptimer-timer";
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status = "disabled";
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};
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};
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lptimer5: timer@50024000 {
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compatible = "st,stm32-lptimer";
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reg = <0x50024000 0x400>;
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interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc LPTIM5_K>;
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clock-names = "mux";
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wakeup-source;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm-lp";
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#pwm-cells = <3>;
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status = "disabled";
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};
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timer {
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compatible = "st,stm32-lptimer-timer";
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status = "disabled";
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};
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};
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mdma: dma-controller@58000000 {
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compatible = "st,stm32h7-mdma";
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reg = <0x58000000 0x1000>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc MDMA>;
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#dma-cells = <5>;
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dma-channels = <32>;
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dma-requests = <48>;
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};
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crc1: crc@58009000 {
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compatible = "st,stm32f7-crc";
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reg = <0x58009000 0x400>;
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clocks = <&rcc CRC1>;
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status = "disabled";
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};
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usbh_ohci: usb@5800c000 {
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compatible = "generic-ohci";
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reg = <0x5800c000 0x1000>;
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clocks = <&usbphyc>, <&rcc USBH>;
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resets = <&rcc USBH_R>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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usbh_ehci: usb@5800d000 {
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compatible = "generic-ehci";
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reg = <0x5800d000 0x1000>;
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clocks = <&usbphyc>, <&rcc USBH>;
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resets = <&rcc USBH_R>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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companion = <&usbh_ohci>;
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status = "disabled";
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};
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iwdg2: watchdog@5a002000 {
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compatible = "st,stm32mp1-iwdg";
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reg = <0x5a002000 0x400>;
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clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
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clock-names = "pclk", "lsi";
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status = "disabled";
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};
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rtc: rtc@5c004000 {
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compatible = "st,stm32mp1-rtc";
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reg = <0x5c004000 0x400>;
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interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scmi_clk CK_SCMI_RTCAPB>,
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<&scmi_clk CK_SCMI_RTC>;
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clock-names = "pclk", "rtc_ck";
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status = "disabled";
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};
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bsec: efuse@5c005000 {
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compatible = "st,stm32mp13-bsec";
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reg = <0x5c005000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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part_number_otp: part_number_otp@4 {
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reg = <0x4 0x2>;
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bits = <0 12>;
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};
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ts_cal1: calib@5c {
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reg = <0x5c 0x2>;
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};
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ts_cal2: calib@5e {
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reg = <0x5e 0x2>;
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};
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};
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etzpc: bus@5c007000 {
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compatible = "simple-bus";
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reg = <0x5c007000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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adc_2: adc@48004000 {
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compatible = "st,stm32mp13-adc-core";
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reg = <0x48004000 0x400>;
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@ -1079,32 +1226,6 @@
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};
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};
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rcc: rcc@50000000 {
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compatible = "st,stm32mp13-rcc", "syscon";
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reg = <0x50000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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clock-names = "hse", "hsi", "csi", "lse", "lsi";
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clocks = <&scmi_clk CK_SCMI_HSE>,
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<&scmi_clk CK_SCMI_HSI>,
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<&scmi_clk CK_SCMI_CSI>,
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<&scmi_clk CK_SCMI_LSE>,
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<&scmi_clk CK_SCMI_LSI>;
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};
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exti: interrupt-controller@5000d000 {
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compatible = "st,stm32mp13-exti", "syscon";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x5000d000 0x400>;
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};
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syscfg: syscon@50020000 {
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compatible = "st,stm32mp157-syscfg", "syscon";
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reg = <0x50020000 0x400>;
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clocks = <&rcc SYSCFG>;
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};
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lptimer2: timer@50021000 {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -1168,48 +1289,6 @@
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};
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};
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lptimer4: timer@50023000 {
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compatible = "st,stm32-lptimer";
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reg = <0x50023000 0x400>;
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interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc LPTIM4_K>;
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clock-names = "mux";
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wakeup-source;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm-lp";
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#pwm-cells = <3>;
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status = "disabled";
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};
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timer {
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compatible = "st,stm32-lptimer-timer";
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status = "disabled";
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};
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};
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lptimer5: timer@50024000 {
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compatible = "st,stm32-lptimer";
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reg = <0x50024000 0x400>;
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interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc LPTIM5_K>;
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clock-names = "mux";
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wakeup-source;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm-lp";
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#pwm-cells = <3>;
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status = "disabled";
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};
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timer {
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compatible = "st,stm32-lptimer-timer";
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status = "disabled";
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};
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};
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hash: hash@54003000 {
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compatible = "st,stm32mp13-hash";
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reg = <0x54003000 0x400>;
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@ -1229,16 +1308,6 @@
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status = "disabled";
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};
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mdma: dma-controller@58000000 {
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compatible = "st,stm32h7-mdma";
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reg = <0x58000000 0x1000>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc MDMA>;
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#dma-cells = <5>;
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dma-channels = <32>;
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dma-requests = <48>;
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};
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fmc: memory-controller@58002000 {
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compatible = "st,stm32mp1-fmc2-ebi";
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reg = <0x58002000 0x1000>;
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@ -1315,40 +1384,6 @@
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status = "disabled";
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};
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crc1: crc@58009000 {
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compatible = "st,stm32f7-crc";
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reg = <0x58009000 0x400>;
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clocks = <&rcc CRC1>;
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status = "disabled";
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};
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usbh_ohci: usb@5800c000 {
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compatible = "generic-ohci";
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reg = <0x5800c000 0x1000>;
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clocks = <&usbphyc>, <&rcc USBH>;
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resets = <&rcc USBH_R>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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usbh_ehci: usb@5800d000 {
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compatible = "generic-ehci";
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reg = <0x5800d000 0x1000>;
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clocks = <&usbphyc>, <&rcc USBH>;
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resets = <&rcc USBH_R>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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companion = <&usbh_ohci>;
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status = "disabled";
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};
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iwdg2: watchdog@5a002000 {
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compatible = "st,stm32mp1-iwdg";
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reg = <0x5a002000 0x400>;
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clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
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clock-names = "pclk", "lsi";
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status = "disabled";
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};
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usbphyc: usbphyc@5a006000 {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -1371,33 +1406,6 @@
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reg = <1>;
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};
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};
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rtc: rtc@5c004000 {
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compatible = "st,stm32mp1-rtc";
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reg = <0x5c004000 0x400>;
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interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scmi_clk CK_SCMI_RTCAPB>,
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<&scmi_clk CK_SCMI_RTC>;
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clock-names = "pclk", "rtc_ck";
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status = "disabled";
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};
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bsec: efuse@5c005000 {
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compatible = "st,stm32mp13-bsec";
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reg = <0x5c005000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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part_number_otp: part_number_otp@4 {
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reg = <0x4 0x2>;
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bits = <0 12>;
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};
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ts_cal1: calib@5c {
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reg = <0x5c 0x2>;
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};
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ts_cal2: calib@5e {
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reg = <0x5e 0x2>;
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};
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};
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/*
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@ -33,7 +33,10 @@
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bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
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status = "disabled";
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};
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};
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};
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&etzpc {
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adc_1: adc@48003000 {
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compatible = "st,stm32mp13-adc-core";
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reg = <0x48003000 0x400>;
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@ -64,5 +67,4 @@
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};
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};
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};
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};
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};
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@ -4,8 +4,7 @@
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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/ {
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soc {
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&etzpc {
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cryp: crypto@54002000 {
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compatible = "st,stm32mp1-cryp";
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reg = <0x54002000 0x400>;
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@ -14,5 +13,4 @@
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resets = <&rcc CRYP1_R>;
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status = "disabled";
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};
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};
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};
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@ -4,8 +4,7 @@
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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/ {
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soc {
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&etzpc {
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cryp: crypto@54002000 {
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compatible = "st,stm32mp1-cryp";
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reg = <0x54002000 0x400>;
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@ -14,5 +13,4 @@
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resets = <&rcc CRYP1_R>;
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status = "disabled";
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};
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};
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};
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