dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator
Add bindings for the Video-Output clock and reset generator (VOUTCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Xingyu Wu
Conor Dooley
parent
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commit
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 Video-Output Clock and Reset Generator
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-voutcrg
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Vout Top core
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- description: Vout Top Ahb
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- description: Vout Top Axi
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- description: Vout Top HDMI MCLK
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- description: I2STX0 BCLK
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- description: external HDMI pixel
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clock-names:
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items:
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- const: vout_src
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- const: vout_top_ahb
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- const: vout_top_axi
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- const: vout_top_hdmitx0_mclk
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- const: i2stx0_bclk
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- const: hdmitx0_pixelclk
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resets:
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maxItems: 1
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description: Vout Top core
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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power-domains:
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maxItems: 1
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description:
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Vout domain power
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- '#clock-cells'
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- '#reset-cells'
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- power-domains
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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#include <dt-bindings/power/starfive,jh7110-pmu.h>
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#include <dt-bindings/reset/starfive,jh7110-crg.h>
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voutcrg: clock-controller@295C0000 {
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compatible = "starfive,jh7110-voutcrg";
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reg = <0x295C0000 0x10000>;
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clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
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<&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
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<&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
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<&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
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<&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
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<&hdmitx0_pixelclk>;
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clock-names = "vout_src", "vout_top_ahb",
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"vout_top_axi", "vout_top_hdmitx0_mclk",
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"i2stx0_bclk", "hdmitx0_pixelclk";
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resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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power-domains = <&pwrc JH7110_PD_VOUT>;
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};
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@ -276,4 +276,26 @@
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#define JH7110_ISPCLK_END 14
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/* VOUTCRG clocks */
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#define JH7110_VOUTCLK_APB 0
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#define JH7110_VOUTCLK_DC8200_PIX 1
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#define JH7110_VOUTCLK_DSI_SYS 2
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#define JH7110_VOUTCLK_TX_ESC 3
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#define JH7110_VOUTCLK_DC8200_AXI 4
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#define JH7110_VOUTCLK_DC8200_CORE 5
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#define JH7110_VOUTCLK_DC8200_AHB 6
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#define JH7110_VOUTCLK_DC8200_PIX0 7
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#define JH7110_VOUTCLK_DC8200_PIX1 8
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#define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD 9
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#define JH7110_VOUTCLK_DSITX_APB 10
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#define JH7110_VOUTCLK_DSITX_SYS 11
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#define JH7110_VOUTCLK_DSITX_DPI 12
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#define JH7110_VOUTCLK_DSITX_TXESC 13
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#define JH7110_VOUTCLK_MIPITX_DPHY_TXESC 14
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#define JH7110_VOUTCLK_HDMI_TX_MCLK 15
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#define JH7110_VOUTCLK_HDMI_TX_BCLK 16
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#define JH7110_VOUTCLK_HDMI_TX_SYS 17
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#define JH7110_VOUTCLK_END 18
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#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
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@ -195,4 +195,20 @@
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#define JH7110_ISPRST_END 12
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/* VOUTCRG resets */
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#define JH7110_VOUTRST_DC8200_AXI 0
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#define JH7110_VOUTRST_DC8200_AHB 1
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#define JH7110_VOUTRST_DC8200_CORE 2
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#define JH7110_VOUTRST_DSITX_DPI 3
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#define JH7110_VOUTRST_DSITX_APB 4
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#define JH7110_VOUTRST_DSITX_RXESC 5
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#define JH7110_VOUTRST_DSITX_SYS 6
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#define JH7110_VOUTRST_DSITX_TXBYTEHS 7
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#define JH7110_VOUTRST_DSITX_TXESC 8
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#define JH7110_VOUTRST_HDMI_TX_HDMI 9
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#define JH7110_VOUTRST_MIPITX_DPHY_SYS 10
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#define JH7110_VOUTRST_MIPITX_DPHY_TXBYTEHS 11
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#define JH7110_VOUTRST_END 12
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#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */
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