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clk: qcom: clk-rcg2: Make sure to not write d=0 to the NMD register

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[ Upstream commit d0696770cef35a1fd16ea2167e2198c18aa6fbfe ]

Sometimes calculation of d value may result in 0 because of the
rounding after integer division. This causes the following error:

[  113.969689] camss_gp1_clk_src: rcg didn't update its configuration.
[  113.969754] WARNING: CPU: 3 PID: 35 at drivers/clk/qcom/clk-rcg2.c:122 update_config+0xc8/0xdc

Make sure that D value is never zero.

Fixes: 7f891faf596e ("clk: qcom: clk-rcg2: Add support for duty-cycle for RCG")
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220612145955.385787-3-nikita@trvn.ru
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Nikita Travkin 2022-06-12 19:59:53 +05:00 committed by Greg Kroah-Hartman
parent 23526845a8
commit a0c4d1ebfa
1 changed files with 6 additions and 3 deletions
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9
drivers/clk/qcom/clk-rcg2.c
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@ -13,6 +13,7 @@
#include <linux/rational.h>
#include <linux/regmap.h>
#include <linux/math64.h>
#include <linux/minmax.h>
#include <linux/slab.h>
#include <asm/div64.h>
@ -461,9 +462,11 @@ static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
/* Calculate 2d value */
d = DIV_ROUND_CLOSEST(n * duty_per * 2, 100);
/* Check bit widths of 2d. If D is too big reduce duty cycle. */
if (d > mask)
d = mask;
/*
* Check bit widths of 2d. If D is too big reduce duty cycle.
* Also make sure it is never zero.
*/
d = clamp_val(d, 1, mask);
if ((d / 2) > (n - m))
d = (n - m) * 2;