sh: intc - add support for SH7785
This patch converts the cpu specific interrupt setup code for sh7785 from intc2 to intc. New vectors are also added to match the information provided by the datasheet. No IRQ/IRL pin vectors are enabled by default. Use plat_irq_setup_pins() to select between IRL and IRQ mode. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
e7bd34a15b
commit
a0e23267d4
@ -72,46 +72,235 @@ static int __init sh7785_devices_setup(void)
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}
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__initcall(sh7785_devices_setup);
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static struct intc2_data intc2_irq_table[] = {
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{ 28, 0, 24, 0, 0, 2 }, /* TMU0 */
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enum {
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UNUSED = 0,
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{ 40, 8, 24, 0, 2, 3 }, /* SCIF0 ERI */
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{ 41, 8, 24, 0, 2, 3 }, /* SCIF0 RXI */
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{ 42, 8, 24, 0, 2, 3 }, /* SCIF0 BRI */
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{ 43, 8, 24, 0, 2, 3 }, /* SCIF0 TXI */
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/* interrupt sources */
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{ 44, 8, 16, 0, 3, 3 }, /* SCIF1 ERI */
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{ 45, 8, 16, 0, 3, 3 }, /* SCIF1 RXI */
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{ 46, 8, 16, 0, 3, 3 }, /* SCIF1 BRI */
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{ 47, 8, 16, 0, 3, 3 }, /* SCIF1 TXI */
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IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
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IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
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IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
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IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
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{ 64, 0x14, 8, 0, 14, 2 }, /* PCIC0 */
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{ 65, 0x14, 0, 0, 15, 2 }, /* PCIC1 */
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{ 66, 0x18, 24, 0, 16, 2 }, /* PCIC2 */
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{ 67, 0x18, 16, 0, 17, 2 }, /* PCIC3 */
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{ 68, 0x18, 8, 0, 18, 2 }, /* PCIC4 */
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IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
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IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
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IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
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IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
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{ 60, 8, 8, 0, 4, 3 }, /* SCIF2 ERI, RXI, BRI, TXI */
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{ 60, 8, 0, 0, 5, 3 }, /* SCIF3 ERI, RXI, BRI, TXI */
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{ 60, 12, 24, 0, 6, 3 }, /* SCIF4 ERI, RXI, BRI, TXI */
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{ 60, 12, 16, 0, 7, 3 }, /* SCIF5 ERI, RXI, BRI, TXI */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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WDT,
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TMU0, TMU1, TMU2, TMU2_TICPI,
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HUDI,
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DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3,
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DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE,
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SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
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SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
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DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
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DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
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HSPI,
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SCIF2, SCIF3, SCIF4, SCIF5,
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PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
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PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
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SIOF,
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MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
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DU,
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GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI,
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TMU3, TMU4, TMU5,
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SSI0, SSI1,
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HAC0, HAC1,
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FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1,
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GPIOI0, GPIOI1, GPIOI2, GPIOI3,
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/* interrupt groups */
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TMU012, DMAC0, SCIF0, SCIF1, DMAC1,
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PCIC5, MMCIF, GDTA, TMU345, FLCTL, GPIO
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};
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static struct intc2_desc intc2_irq_desc __read_mostly = {
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.prio_base = 0xffd40000,
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.msk_base = 0xffd40038,
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.mskclr_base = 0xffd4003c,
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.intc2_data = intc2_irq_table,
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.nr_irqs = ARRAY_SIZE(intc2_irq_table),
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.chip = {
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.name = "INTC2-sh7785",
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},
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static struct intc_vect vectors[] = {
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INTC_VECT(WDT, 0x560),
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INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
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INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
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INTC_VECT(HUDI, 0x600),
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INTC_VECT(DMAC0_DMINT0, 0x620), INTC_VECT(DMAC0_DMINT1, 0x640),
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INTC_VECT(DMAC0_DMINT2, 0x660), INTC_VECT(DMAC0_DMINT3, 0x680),
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INTC_VECT(DMAC0_DMINT4, 0x6a0), INTC_VECT(DMAC0_DMINT5, 0x6c0),
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INTC_VECT(DMAC0_DMAE, 0x6e0),
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INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
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INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
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INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
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INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
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INTC_VECT(DMAC1_DMINT6, 0x880), INTC_VECT(DMAC1_DMINT7, 0x8a0),
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INTC_VECT(DMAC1_DMINT8, 0x8c0), INTC_VECT(DMAC1_DMINT9, 0x8e0),
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INTC_VECT(DMAC1_DMINT10, 0x900), INTC_VECT(DMAC1_DMINT11, 0x920),
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INTC_VECT(DMAC1_DMAE, 0x940),
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INTC_VECT(HSPI, 0x960),
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INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
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INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
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INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
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INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
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INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0),
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INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0),
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INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20),
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INTC_VECT(SIOF, 0xc00),
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INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20),
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INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60),
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INTC_VECT(DU, 0xd80),
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INTC_VECT(GDTA_GACLI, 0xda0), INTC_VECT(GDTA_GAMCI, 0xdc0),
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INTC_VECT(GDTA_GAERI, 0xde0),
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INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
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INTC_VECT(TMU5, 0xe40),
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INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
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INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
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INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20),
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INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60),
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INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0),
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INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
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};
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static struct intc_group groups[] = {
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INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
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INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
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DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
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INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
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INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
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INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
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DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE),
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INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
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INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
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INTC_GROUP(GDTA, GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI),
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INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
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INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
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FLCTL_FLTRQ0, FLCTL_FLTRQ1),
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INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
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};
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static struct intc_prio priorities[] = {
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INTC_PRIO(SCIF0, 3),
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INTC_PRIO(SCIF1, 3),
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INTC_PRIO(SCIF2, 3),
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INTC_PRIO(SCIF3, 3),
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INTC_PRIO(SCIF4, 3),
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INTC_PRIO(SCIF5, 3),
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};
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static struct intc_mask_reg mask_registers[] = {
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{ 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
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{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
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{ 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
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{ IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
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IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
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IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
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IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
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IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
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IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
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IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
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IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
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{ 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
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{ 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
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FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
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PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
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SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
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};
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static struct intc_prio_reg prio_registers[] = {
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{ 0xffd00010, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
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IRQ4, IRQ5, IRQ6, IRQ7 } },
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{ 0xffd40000, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, TMU2, TMU2_TICPI } },
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{ 0xffd40004, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
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{ 0xffd40008, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
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{ 0xffd4000c, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
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{ 0xffd40010, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
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{ 0xffd40014, 32, 8, /* INT2PRI5 */ { HAC0, HAC1, PCISERR, PCIINTA } },
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{ 0xffd40018, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
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PCIINTD, PCIC5 } },
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{ 0xffd4001c, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
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{ 0xffd40020, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
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{ 0xffd40024, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
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};
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static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups, priorities,
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mask_registers, prio_registers, NULL);
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/* Support for external interrupt pins in IRQ mode */
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static struct intc_vect vectors_irq0123[] = {
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INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
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INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
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};
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static struct intc_vect vectors_irq4567[] = {
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INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
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INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
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};
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static struct intc_sense_reg sense_registers[] = {
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{ 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
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IRQ4, IRQ5, IRQ6, IRQ7 } },
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};
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static DECLARE_INTC_DESC(intc_desc_irq0123, "sh7785-irq0123", vectors_irq0123,
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NULL, NULL, mask_registers, prio_registers,
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sense_registers);
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static DECLARE_INTC_DESC(intc_desc_irq4567, "sh7785-irq4567", vectors_irq4567,
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NULL, NULL, mask_registers, prio_registers,
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sense_registers);
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/* External interrupt pins in IRL mode */
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static struct intc_vect vectors_irl0123[] = {
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INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
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INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
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INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
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INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
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INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
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INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
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INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
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INTC_VECT(IRL0_HHHL, 0x3c0),
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};
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static struct intc_vect vectors_irl4567[] = {
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INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
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INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
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INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
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INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
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INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
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INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
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INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
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INTC_VECT(IRL4_HHHL, 0xcc0),
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};
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static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
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NULL, NULL, mask_registers, NULL, NULL);
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static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
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NULL, NULL, mask_registers, NULL, NULL);
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void __init plat_irq_setup(void)
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{
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register_intc2_controller(&intc2_irq_desc);
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register_intc_controller(&intc_desc);
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}
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void __init plat_irq_setup_pins(int mode)
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{
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switch (mode) {
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case IRQ_MODE_IRQ7654:
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register_intc_controller(&intc_desc_irq4567);
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break;
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case IRQ_MODE_IRQ3210:
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register_intc_controller(&intc_desc_irq0123);
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break;
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case IRQ_MODE_IRL7654:
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register_intc_controller(&intc_desc_irl4567);
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break;
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case IRQ_MODE_IRL3210:
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register_intc_controller(&intc_desc_irl0123);
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break;
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default:
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BUG();
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}
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}
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@ -192,7 +192,7 @@ config CPU_SUBTYPE_SH7785
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bool "Support SH7785 processor"
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select CPU_SH4A
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select CPU_SHX2
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select CPU_HAS_INTC2_IRQ
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select CPU_HAS_INTC_IRQ
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config CPU_SUBTYPE_SHX3
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bool "Support SH-X3 processor"
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@ -115,7 +115,8 @@ void __init register_intc_controller(struct intc_desc *desc);
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void __init plat_irq_setup(void);
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enum { IRQ_MODE_IRQ, IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
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enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
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IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
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void __init plat_irq_setup_pins(int mode);
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#endif /* __ASM_SH_HW_IRQ_H */
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