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sh, perf: Use common PMU interrupt disabled code

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Transition to using the new generic PERF_PMU_CAP_NO_INTERRUPT method for
failing a sampling event when no PMU interrupt is available.

Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: linux-sh@vger.kernel.org
Link: http://lkml.kernel.org/r/alpine.DEB.2.10.1406150205300.16738@vincent-weaver-1.umelst.maine.edu
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Vince Weaver 2014-06-15 02:06:15 -04:00 committed by Ingo Molnar
parent 97b1198fec
commit a10d60c08c
1 changed files with 7 additions and 8 deletions
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15
arch/sh/kernel/perf_event.c
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@ -128,14 +128,6 @@ static int __hw_perf_event_init(struct perf_event *event)
if (!sh_pmu_initialized()) if (!sh_pmu_initialized())
return -ENODEV; return -ENODEV;
/*
* All of the on-chip counters are "limited", in that they have
* no interrupts, and are therefore unable to do sampling without
* further work and timer assistance.
*/
if (hwc->sample_period)
return -EINVAL;
/* /*
* See if we need to reserve the counter. * See if we need to reserve the counter.
* *
@ -392,6 +384,13 @@ int register_sh_pmu(struct sh_pmu *_pmu)
pr_info("Performance Events: %s support registered\n", _pmu->name); pr_info("Performance Events: %s support registered\n", _pmu->name);
/*
* All of the on-chip counters are "limited", in that they have
* no interrupts, and are therefore unable to do sampling without
* further work and timer assistance.
*/
pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
WARN_ON(_pmu->num_events > MAX_HWEVENTS); WARN_ON(_pmu->num_events > MAX_HWEVENTS);
perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);