irqchip/sifive-plic: Cleanup PLIC contexts upon irqdomain creation failure
The SiFive PLIC contexts should not be left dangling if irqdomain creation fails because plic_starting_cpu() can crash accessing unmapped registers. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240222094006.1030709-6-apatel@ventanamicro.com
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6c725f33d6
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a15587277a
@ -417,17 +417,45 @@ static const struct of_device_id plic_match[] = {
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{}
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};
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static int plic_parse_context_parent(struct platform_device *pdev, u32 context,
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u32 *parent_hwirq, int *parent_cpu)
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{
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struct device *dev = &pdev->dev;
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struct of_phandle_args parent;
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unsigned long hartid;
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int rc;
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/*
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* Currently, only OF fwnode is supported so extend this
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* function for ACPI support.
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*/
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if (!is_of_node(dev->fwnode))
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return -EINVAL;
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rc = of_irq_parse_one(to_of_node(dev->fwnode), context, &parent);
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if (rc)
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return rc;
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rc = riscv_of_parent_hartid(parent.np, &hartid);
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if (rc)
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return rc;
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*parent_hwirq = parent.args[0];
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*parent_cpu = riscv_hartid_to_cpuid(hartid);
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return 0;
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}
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static int plic_probe(struct platform_device *pdev)
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{
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int error = 0, nr_contexts, nr_handlers = 0, i;
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int error = 0, nr_contexts, nr_handlers = 0, cpu, i;
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struct device *dev = &pdev->dev;
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unsigned long plic_quirks = 0;
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struct plic_handler *handler;
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u32 nr_irqs, parent_hwirq;
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struct irq_domain *domain;
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struct plic_priv *priv;
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irq_hw_number_t hwirq;
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bool cpuhp_setup;
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unsigned int cpu;
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u32 nr_irqs;
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if (is_of_node(dev->fwnode)) {
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const struct of_device_id *id;
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@ -463,13 +491,9 @@ static int plic_probe(struct platform_device *pdev)
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return -EINVAL;
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for (i = 0; i < nr_contexts; i++) {
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struct of_phandle_args parent;
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irq_hw_number_t hwirq;
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int cpu;
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unsigned long hartid;
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if (of_irq_parse_one(to_of_node(dev->fwnode), i, &parent)) {
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dev_err(dev, "failed to parse parent for context %d.\n", i);
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error = plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu);
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if (error) {
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dev_warn(dev, "hwirq for context%d not found\n", i);
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continue;
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}
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@ -477,7 +501,7 @@ static int plic_probe(struct platform_device *pdev)
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* Skip contexts other than external interrupts for our
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* privilege level.
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*/
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if (parent.args[0] != RV_IRQ_EXT) {
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if (parent_hwirq != RV_IRQ_EXT) {
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/* Disable S-mode enable bits if running in M-mode. */
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if (IS_ENABLED(CONFIG_RISCV_M_MODE)) {
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void __iomem *enable_base = priv->regs +
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@ -490,13 +514,6 @@ static int plic_probe(struct platform_device *pdev)
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continue;
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}
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error = riscv_of_parent_hartid(parent.np, &hartid);
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if (error < 0) {
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dev_warn(dev, "failed to parse hart ID for context %d.\n", i);
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continue;
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}
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cpu = riscv_hartid_to_cpuid(hartid);
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if (cpu < 0) {
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dev_warn(dev, "Invalid cpuid for context %d\n", i);
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continue;
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@ -534,7 +551,7 @@ static int plic_probe(struct platform_device *pdev)
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handler->enable_save = devm_kcalloc(dev, DIV_ROUND_UP(nr_irqs, 32),
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sizeof(*handler->enable_save), GFP_KERNEL);
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if (!handler->enable_save)
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return -ENOMEM;
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goto fail_cleanup_contexts;
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done:
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for (hwirq = 1; hwirq <= nr_irqs; hwirq++) {
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plic_toggle(handler, hwirq, 0);
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@ -547,7 +564,7 @@ done:
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priv->irqdomain = irq_domain_add_linear(to_of_node(dev->fwnode), nr_irqs + 1,
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&plic_irqdomain_ops, priv);
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if (WARN_ON(!priv->irqdomain))
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return -ENOMEM;
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goto fail_cleanup_contexts;
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/*
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* We can have multiple PLIC instances so setup cpuhp state
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@ -575,6 +592,22 @@ done:
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dev_info(dev, "mapped %d interrupts with %d handlers for %d contexts.\n",
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nr_irqs, nr_handlers, nr_contexts);
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return 0;
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fail_cleanup_contexts:
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for (i = 0; i < nr_contexts; i++) {
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if (plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu))
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continue;
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if (parent_hwirq != RV_IRQ_EXT || cpu < 0)
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continue;
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handler = per_cpu_ptr(&plic_handlers, cpu);
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handler->present = false;
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handler->hart_base = NULL;
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handler->enable_base = NULL;
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handler->enable_save = NULL;
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handler->priv = NULL;
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}
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return -ENOMEM;
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}
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static struct platform_driver plic_driver = {
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