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net/mlx5: DR, Add HW bits and definitions for Geneve flex parser

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Add definition for flex parser tunneling header for Geneve.

Signed-off-by: Yevgeny Kliteynik <kliteyn@mellanox.com>
Reviewed-by: Alex Vesker <valex@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
This commit is contained in:
Yevgeny Kliteynik 2019-10-28 16:58:53 +02:00 committed by Saeed Mahameed
parent 6e9e286e4a
commit a18fab48db
2 changed files with 14 additions and 0 deletions
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13
drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr.h
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@ -559,6 +559,19 @@ struct mlx5_ifc_ste_flex_parser_tnl_vxlan_gpe_bits {
u8 reserved_at_40[0x40];
};
struct mlx5_ifc_ste_flex_parser_tnl_geneve_bits {
u8 reserved_at_0[0x2];
u8 geneve_opt_len[0x6];
u8 geneve_oam[0x1];
u8 reserved_at_9[0x7];
u8 geneve_protocol_type[0x10];
u8 geneve_vni[0x18];
u8 reserved_at_38[0x8];
u8 reserved_at_40[0x40];
};
struct mlx5_ifc_ste_general_purpose_bits {
u8 general_purpose_lookup_field[0x20];

1
include/linux/mlx5/mlx5_ifc.h
View File

@ -1110,6 +1110,7 @@ enum {
};
enum {
MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3,
MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,