From a19220fa5f1a740d98654ee1d6cf11a8e0158018 Mon Sep 17 00:00:00 2001 From: Lucas De Marchi Date: Mon, 13 Mar 2023 17:30:04 -0700 Subject: [PATCH] drm/xe: Add PVC gt workarounds Synchronize with i915 the PVC gt workarounds as of committ commit 4d14d7717f19 ("drm/i915/selftest: Fix ktime_get() and h/w access order"). v2: Add masked flag to XEHPC_LNCFMISCCFGREG0 (Matt Roper) Signed-off-by: Lucas De Marchi Reviewed-by: Matt Roper Link: https://lore.kernel.org/r/20230314003012.2600353-7-lucas.demarchi@intel.com Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/regs/xe_gt_regs.h | 9 +++++++++ drivers/gpu/drm/xe/xe_wa.c | 19 +++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index d3b862e4cd0d..411cdbae1894 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -216,6 +216,15 @@ #define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4) #define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4) +#define XEHPC_LNCFMISCCFGREG0 MCR_REG(0xb01c) +#define XEHPC_OVRLSCCC REG_BIT(0) + +#define RENDER_MOD_CTRL MCR_REG(0xcf2c) +#define COMP_MOD_CTRL MCR_REG(0xcf30) +#define XEHP_VDBX_MOD_CTRL MCR_REG(0xcf34) +#define XEHP_VEBX_MOD_CTRL MCR_REG(0xcf38) +#define FORCE_MISS_FTLB REG_BIT(3) + #define GEN10_SAMPLER_MODE MCR_REG(0xe18c) #define ENABLE_SMALLPL REG_BIT(15) #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index 155cabe16e2e..e8d523033b87 100644 --- a/drivers/gpu/drm/xe/xe_wa.c +++ b/drivers/gpu/drm/xe/xe_wa.c @@ -180,6 +180,25 @@ static const struct xe_rtp_entry gt_was[] = { XE_RTP_RULES(PLATFORM(DG2)), XE_RTP_ACTIONS(CLR(GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE)) }, + + /* PVC */ + + { XE_RTP_NAME("14015795083"), + XE_RTP_RULES(PLATFORM(PVC)), + XE_RTP_ACTIONS(CLR(GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE)) + }, + { XE_RTP_NAME("18018781329"), + XE_RTP_RULES(PLATFORM(PVC)), + XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), + SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), + SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), + SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) + }, + { XE_RTP_NAME("16016694945"), + XE_RTP_RULES(PLATFORM(PVC)), + XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC, + XE_RTP_ACTION_FLAG(MASKED_REG))) + }, {} };