cxgb4: collect MC memory dump
Use meminfo to get base address and size of MC memory. Also use same meminfo for EDC memory dumps. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -18,17 +18,14 @@
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#ifndef __CUDBG_ENTITY_H__
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#define __CUDBG_ENTITY_H__
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#define EDC0_FLAG 3
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#define EDC1_FLAG 4
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#define EDC0_FLAG 0
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#define EDC1_FLAG 1
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#define MC_FLAG 2
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#define MC0_FLAG 3
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#define MC1_FLAG 4
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#define CUDBG_ENTITY_SIGNATURE 0xCCEDB001
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struct card_mem {
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u16 size_edc0;
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u16 size_edc1;
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u16 mem_flag;
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};
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struct cudbg_mbox_log {
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struct mbox_cmd entry;
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u32 hi[MBOX_LEN / 8];
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@ -47,6 +47,8 @@ enum cudbg_dbg_entity_type {
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CUDBG_CIM_OBQ_NCSI = 17,
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CUDBG_EDC0 = 18,
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CUDBG_EDC1 = 19,
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CUDBG_MC0 = 20,
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CUDBG_MC1 = 21,
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CUDBG_RSS = 22,
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CUDBG_RSS_VF_CONF = 25,
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CUDBG_PATH_MTU = 27,
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@ -682,6 +682,42 @@ int cudbg_collect_obq_sge_rx_q1(struct cudbg_init *pdbg_init,
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return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 7);
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}
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static int cudbg_meminfo_get_mem_index(struct adapter *padap,
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struct cudbg_meminfo *mem_info,
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u8 mem_type, u8 *idx)
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{
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u8 i, flag;
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switch (mem_type) {
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case MEM_EDC0:
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flag = EDC0_FLAG;
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break;
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case MEM_EDC1:
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flag = EDC1_FLAG;
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break;
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case MEM_MC0:
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/* Some T5 cards have both MC0 and MC1. */
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flag = is_t5(padap->params.chip) ? MC0_FLAG : MC_FLAG;
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break;
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case MEM_MC1:
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flag = MC1_FLAG;
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break;
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default:
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return CUDBG_STATUS_ENTITY_NOT_FOUND;
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}
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for (i = 0; i < mem_info->avail_c; i++) {
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if (mem_info->avail[i].idx == flag) {
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*idx = i;
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return 0;
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}
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}
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return CUDBG_STATUS_ENTITY_NOT_FOUND;
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}
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#define CUDBG_YIELD_ITERATION 256
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static int cudbg_read_fw_mem(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff, u8 mem_type,
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unsigned long tot_len,
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@ -690,10 +726,20 @@ static int cudbg_read_fw_mem(struct cudbg_init *pdbg_init,
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unsigned long bytes, bytes_left, bytes_read = 0;
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struct adapter *padap = pdbg_init->adap;
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struct cudbg_buffer temp_buff = { 0 };
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u32 yield_count = 0;
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int rc = 0;
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bytes_left = tot_len;
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while (bytes_left > 0) {
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/* As MC size is huge and read through PIO access, this
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* loop will hold cpu for a longer time. OS may think that
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* the process is hanged and will generate CPU stall traces.
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* So yield the cpu regularly.
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*/
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yield_count++;
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if (!(yield_count % CUDBG_YIELD_ITERATION))
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schedule();
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bytes = min_t(unsigned long, bytes_left,
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(unsigned long)CUDBG_CHUNK_SIZE);
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rc = cudbg_get_buff(dbg_buff, bytes, &temp_buff);
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@ -717,27 +763,6 @@ static int cudbg_read_fw_mem(struct cudbg_init *pdbg_init,
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return rc;
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}
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static void cudbg_collect_mem_info(struct cudbg_init *pdbg_init,
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struct card_mem *mem_info)
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{
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struct adapter *padap = pdbg_init->adap;
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u32 value;
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value = t4_read_reg(padap, MA_EDRAM0_BAR_A);
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value = EDRAM0_SIZE_G(value);
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mem_info->size_edc0 = (u16)value;
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value = t4_read_reg(padap, MA_EDRAM1_BAR_A);
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value = EDRAM1_SIZE_G(value);
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mem_info->size_edc1 = (u16)value;
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value = t4_read_reg(padap, MA_TARGET_MEM_ENABLE_A);
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if (value & EDRAM0_ENABLE_F)
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mem_info->mem_flag |= (1 << EDC0_FLAG);
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if (value & EDRAM1_ENABLE_F)
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mem_info->mem_flag |= (1 << EDC1_FLAG);
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}
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static void cudbg_t4_fwcache(struct cudbg_init *pdbg_init,
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struct cudbg_error *cudbg_err)
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{
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@ -757,37 +782,25 @@ static int cudbg_collect_mem_region(struct cudbg_init *pdbg_init,
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struct cudbg_error *cudbg_err,
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u8 mem_type)
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{
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struct card_mem mem_info = {0};
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unsigned long flag, size;
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struct adapter *padap = pdbg_init->adap;
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struct cudbg_meminfo mem_info;
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unsigned long size;
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u8 mc_idx;
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int rc;
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cudbg_t4_fwcache(pdbg_init, cudbg_err);
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cudbg_collect_mem_info(pdbg_init, &mem_info);
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switch (mem_type) {
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case MEM_EDC0:
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flag = (1 << EDC0_FLAG);
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size = cudbg_mbytes_to_bytes(mem_info.size_edc0);
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break;
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case MEM_EDC1:
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flag = (1 << EDC1_FLAG);
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size = cudbg_mbytes_to_bytes(mem_info.size_edc1);
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break;
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default:
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rc = CUDBG_STATUS_ENTITY_NOT_FOUND;
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goto err;
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}
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memset(&mem_info, 0, sizeof(struct cudbg_meminfo));
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rc = cudbg_fill_meminfo(padap, &mem_info);
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if (rc)
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return rc;
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if (mem_info.mem_flag & flag) {
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rc = cudbg_read_fw_mem(pdbg_init, dbg_buff, mem_type,
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size, cudbg_err);
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if (rc)
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goto err;
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} else {
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rc = CUDBG_STATUS_ENTITY_NOT_FOUND;
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goto err;
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}
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err:
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return rc;
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cudbg_t4_fwcache(pdbg_init, cudbg_err);
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rc = cudbg_meminfo_get_mem_index(padap, &mem_info, mem_type, &mc_idx);
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if (rc)
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return rc;
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size = mem_info.avail[mc_idx].limit - mem_info.avail[mc_idx].base;
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return cudbg_read_fw_mem(pdbg_init, dbg_buff, mem_type, size,
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cudbg_err);
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}
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int cudbg_collect_edc0_meminfo(struct cudbg_init *pdbg_init,
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@ -806,6 +819,22 @@ int cudbg_collect_edc1_meminfo(struct cudbg_init *pdbg_init,
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MEM_EDC1);
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}
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int cudbg_collect_mc0_meminfo(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err)
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{
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return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
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MEM_MC0);
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}
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int cudbg_collect_mc1_meminfo(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err)
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{
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return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
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MEM_MC1);
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}
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int cudbg_collect_rss(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err)
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@ -75,6 +75,12 @@ int cudbg_collect_edc0_meminfo(struct cudbg_init *pdbg_init,
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int cudbg_collect_edc1_meminfo(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err);
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int cudbg_collect_mc0_meminfo(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err);
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int cudbg_collect_mc1_meminfo(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err);
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int cudbg_collect_rss(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err);
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@ -22,6 +22,8 @@
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static const struct cxgb4_collect_entity cxgb4_collect_mem_dump[] = {
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{ CUDBG_EDC0, cudbg_collect_edc0_meminfo },
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{ CUDBG_EDC1, cudbg_collect_edc1_meminfo },
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{ CUDBG_MC0, cudbg_collect_mc0_meminfo },
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{ CUDBG_MC1, cudbg_collect_mc1_meminfo },
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};
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static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = {
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@ -158,6 +160,22 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
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}
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len = cudbg_mbytes_to_bytes(len);
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break;
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case CUDBG_MC0:
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value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
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if (value & EXT_MEM0_ENABLE_F) {
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value = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
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len = EXT_MEM0_SIZE_G(value);
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}
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len = cudbg_mbytes_to_bytes(len);
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break;
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case CUDBG_MC1:
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value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
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if (value & EXT_MEM1_ENABLE_F) {
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value = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
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len = EXT_MEM1_SIZE_G(value);
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}
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len = cudbg_mbytes_to_bytes(len);
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break;
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case CUDBG_RSS:
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len = RSS_NENTRIES * sizeof(u16);
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break;
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