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PCI: cadence: Allow PTM Responder to be enabled

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This enables the Controller [RP] to automatically respond with
Response/ResponseD messages if CDNS_PCIE_LM_TPM_CTRL_PTMRSEN
and PCI_PTM_CTRL_ENABLE bits are both set.

Link: https://lore.kernel.org/r/20220512055539.1782437-1-christian.gmeiner@gmail.com
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
This commit is contained in:
Christian Gmeiner 2022-05-12 07:55:38 +02:00 committed by Lorenzo Pieralisi
parent 0aa3a0937f
commit a1f67bc131
2 changed files with 14 additions and 0 deletions
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10
drivers/pci/controller/cadence/pcie-cadence-host.c
View File

@ -123,6 +123,14 @@ static int cdns_pcie_retrain(struct cdns_pcie *pcie)
return ret; return ret;
} }
static void cdns_pcie_host_enable_ptm_response(struct cdns_pcie *pcie)
{
u32 val;
val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_PTM_CTRL);
cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL_PTMRSEN);
}
static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc) static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc)
{ {
struct cdns_pcie *pcie = &rc->pcie; struct cdns_pcie *pcie = &rc->pcie;
@ -501,6 +509,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
if (rc->quirk_detect_quiet_flag) if (rc->quirk_detect_quiet_flag)
cdns_pcie_detect_quiet_min_delay_set(&rc->pcie); cdns_pcie_detect_quiet_min_delay_set(&rc->pcie);
cdns_pcie_host_enable_ptm_response(pcie);
ret = cdns_pcie_start_link(pcie); ret = cdns_pcie_start_link(pcie);
if (ret) { if (ret) {
dev_err(dev, "Failed to start link\n"); dev_err(dev, "Failed to start link\n");

4
drivers/pci/controller/cadence/pcie-cadence.h
View File

@ -116,6 +116,10 @@
#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ #define LM_RC_BAR_CFG_APERTURE(bar, aperture) \
(((aperture) - 2) << ((bar) * 8)) (((aperture) - 2) << ((bar) * 8))
/* PTM Control Register */
#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0da8)
#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17)
/* /*
* Endpoint Function Registers (PCI configuration space for endpoint functions) * Endpoint Function Registers (PCI configuration space for endpoint functions)
*/ */