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platform/x86: pmc_atom: Annotate d3_sts register bit defines

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The include/linux/platform_data/x86/pmc_atom.h d3_sts register bit defines
are named after how these bits are used on Bay Trail devices.

On Cherry Trail (CHT) devices some of these bits have a different meaning
according to the datasheet.

At a comment to the defines for bits which have a different meaning
on Cherry Trail devices.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20240305105915.76242-3-hdegoede@redhat.com
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
This commit is contained in:
Hans de Goede 2024-03-05 11:59:12 +01:00 committed by Ilpo Järvinen
parent dbab9afe86
commit a21ff5a0a7
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1 changed files with 6 additions and 6 deletions
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12
include/linux/platform_data/x86/pmc_atom.h
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@ -117,14 +117,14 @@
#define BIT_SCC_SDIO BIT(9)
#define BIT_SCC_SDCARD BIT(10)
#define BIT_SCC_MIPI BIT(11)
#define BIT_HDA BIT(12)
#define BIT_HDA BIT(12) /* CHT datasheet: reserved */
#define BIT_LPE BIT(13)
#define BIT_OTG BIT(14)
#define BIT_USH BIT(15)
#define BIT_GBE BIT(16)
#define BIT_SATA BIT(17)
#define BIT_USB_EHCI BIT(18)
#define BIT_SEC BIT(19)
#define BIT_USH BIT(15) /* CHT datasheet: reserved */
#define BIT_GBE BIT(16) /* CHT datasheet: reserved */
#define BIT_SATA BIT(17) /* CHT datasheet: reserved */
#define BIT_USB_EHCI BIT(18) /* CHT datasheet: XHCI! */
#define BIT_SEC BIT(19) /* BYT datasheet: reserved */
#define BIT_PCIE_PORT0 BIT(20)
#define BIT_PCIE_PORT1 BIT(21)
#define BIT_PCIE_PORT2 BIT(22)