drm/komeda: Add komeda_crtc_mode_valid/fixup
komeda_crtc_mode_valid compares the input mode->clk with main engine clk and AXI clk, and reject the mode if the required pixel clk can not be satisfied by main engine clk and AXI-clk. Signed-off-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
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@ -94,9 +94,61 @@ komeda_crtc_atomic_flush(struct drm_crtc *crtc,
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komeda_crtc_do_flush(crtc, old);
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}
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static enum drm_mode_status
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komeda_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *m)
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{
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struct komeda_dev *mdev = crtc->dev->dev_private;
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struct komeda_crtc *kcrtc = to_kcrtc(crtc);
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struct komeda_pipeline *master = kcrtc->master;
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long mode_clk, pxlclk;
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if (m->flags & DRM_MODE_FLAG_INTERLACE)
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return MODE_NO_INTERLACE;
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/* main clock/AXI clk must be faster than pxlclk*/
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mode_clk = m->clock * 1000;
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pxlclk = clk_round_rate(master->pxlclk, mode_clk);
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if (pxlclk != mode_clk) {
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DRM_DEBUG_ATOMIC("pxlclk doesn't support %ld Hz\n", mode_clk);
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return MODE_NOCLOCK;
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}
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if (clk_round_rate(mdev->mclk, mode_clk) < pxlclk) {
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DRM_DEBUG_ATOMIC("mclk can't satisfy the requirement of %s-clk: %ld.\n",
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m->name, pxlclk);
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return MODE_CLOCK_HIGH;
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}
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if (clk_round_rate(master->aclk, mode_clk) < pxlclk) {
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DRM_DEBUG_ATOMIC("aclk can't satisfy the requirement of %s-clk: %ld.\n",
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m->name, pxlclk);
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return MODE_CLOCK_HIGH;
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}
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return MODE_OK;
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}
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static bool komeda_crtc_mode_fixup(struct drm_crtc *crtc,
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const struct drm_display_mode *m,
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struct drm_display_mode *adjusted_mode)
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{
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struct komeda_crtc *kcrtc = to_kcrtc(crtc);
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struct komeda_pipeline *master = kcrtc->master;
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long mode_clk = m->clock * 1000;
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adjusted_mode->clock = clk_round_rate(master->pxlclk, mode_clk) / 1000;
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return true;
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}
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struct drm_crtc_helper_funcs komeda_crtc_helper_funcs = {
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.atomic_check = komeda_crtc_atomic_check,
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.atomic_flush = komeda_crtc_atomic_flush,
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.mode_valid = komeda_crtc_mode_valid,
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.mode_fixup = komeda_crtc_mode_fixup,
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};
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static const struct drm_crtc_funcs komeda_crtc_funcs = {
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