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drm/imagination: Add FWIF headers

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Changes since v8:
- Corrected license identifiers

Changes since v7:
- Add padding to struct rogue_fwif_ccb_ctl to place read and write offsets
  in different cache lines

Changes since v5:
- Split up header commit due to size
- Add BRN 71242 to device info

Changes since v4:
- Add FW header device info

Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Signed-off-by: Donald Robson <donald.robson@imgtec.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/aa681533a02bd2d46af17a6a6010f4d6048fbb0a.1700668843.git.donald.robson@imgtec.com
Signed-off-by: Maxime Ripard <mripard@kernel.org>
This commit is contained in:
Sarah Walker 2023-11-22 16:34:30 +00:00 committed by Maxime Ripard
parent 7900e00434
commit a26f067fea
No known key found for this signature in database
GPG Key ID: E3EF0D6F671851C5
10 changed files with 3832 additions and 0 deletions
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2188
drivers/gpu/drm/imagination/pvr_rogue_fwif.h Normal file
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File diff suppressed because it is too large Load Diff

493
drivers/gpu/drm/imagination/pvr_rogue_fwif_check.h Normal file
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@ -0,0 +1,493 @@
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/* Copyright (c) 2023 Imagination Technologies Ltd. */
#ifndef PVR_ROGUE_FWIF_CHECK_H
#define PVR_ROGUE_FWIF_CHECK_H
#include <linux/build_bug.h>
#define OFFSET_CHECK(type, member, offset) \
static_assert(offsetof(type, member) == (offset), \
"offsetof(" #type ", " #member ") incorrect")
#define SIZE_CHECK(type, size) \
static_assert(sizeof(type) == (size), #type " is incorrect size")
OFFSET_CHECK(struct rogue_fwif_file_info_buf, path, 0);
OFFSET_CHECK(struct rogue_fwif_file_info_buf, info, 200);
OFFSET_CHECK(struct rogue_fwif_file_info_buf, line_num, 400);
SIZE_CHECK(struct rogue_fwif_file_info_buf, 408);
OFFSET_CHECK(struct rogue_fwif_tracebuf_space, trace_pointer, 0);
OFFSET_CHECK(struct rogue_fwif_tracebuf_space, trace_buffer_fw_addr, 4);
OFFSET_CHECK(struct rogue_fwif_tracebuf_space, trace_buffer, 8);
OFFSET_CHECK(struct rogue_fwif_tracebuf_space, assert_buf, 16);
SIZE_CHECK(struct rogue_fwif_tracebuf_space, 424);
OFFSET_CHECK(struct rogue_fwif_tracebuf, log_type, 0);
OFFSET_CHECK(struct rogue_fwif_tracebuf, tracebuf, 8);
OFFSET_CHECK(struct rogue_fwif_tracebuf, tracebuf_size_in_dwords, 856);
OFFSET_CHECK(struct rogue_fwif_tracebuf, tracebuf_flags, 860);
SIZE_CHECK(struct rogue_fwif_tracebuf, 864);
OFFSET_CHECK(struct rogue_fw_fault_info, cr_timer, 0);
OFFSET_CHECK(struct rogue_fw_fault_info, os_timer, 8);
OFFSET_CHECK(struct rogue_fw_fault_info, data, 16);
OFFSET_CHECK(struct rogue_fw_fault_info, reserved, 20);
OFFSET_CHECK(struct rogue_fw_fault_info, fault_buf, 24);
SIZE_CHECK(struct rogue_fw_fault_info, 432);
OFFSET_CHECK(struct rogue_fwif_sysdata, config_flags, 0);
OFFSET_CHECK(struct rogue_fwif_sysdata, config_flags_ext, 4);
OFFSET_CHECK(struct rogue_fwif_sysdata, pow_state, 8);
OFFSET_CHECK(struct rogue_fwif_sysdata, hw_perf_ridx, 12);
OFFSET_CHECK(struct rogue_fwif_sysdata, hw_perf_widx, 16);
OFFSET_CHECK(struct rogue_fwif_sysdata, hw_perf_wrap_count, 20);
OFFSET_CHECK(struct rogue_fwif_sysdata, hw_perf_size, 24);
OFFSET_CHECK(struct rogue_fwif_sysdata, hw_perf_drop_count, 28);
OFFSET_CHECK(struct rogue_fwif_sysdata, hw_perf_ut, 32);
OFFSET_CHECK(struct rogue_fwif_sysdata, first_drop_ordinal, 36);
OFFSET_CHECK(struct rogue_fwif_sysdata, last_drop_ordinal, 40);
OFFSET_CHECK(struct rogue_fwif_sysdata, os_runtime_flags_mirror, 44);
OFFSET_CHECK(struct rogue_fwif_sysdata, fault_info, 80);
OFFSET_CHECK(struct rogue_fwif_sysdata, fw_faults, 3536);
OFFSET_CHECK(struct rogue_fwif_sysdata, cr_poll_addr, 3540);
OFFSET_CHECK(struct rogue_fwif_sysdata, cr_poll_mask, 3548);
OFFSET_CHECK(struct rogue_fwif_sysdata, cr_poll_count, 3556);
OFFSET_CHECK(struct rogue_fwif_sysdata, start_idle_time, 3568);
OFFSET_CHECK(struct rogue_fwif_sysdata, hwr_state_flags, 3576);
OFFSET_CHECK(struct rogue_fwif_sysdata, hwr_recovery_flags, 3580);
OFFSET_CHECK(struct rogue_fwif_sysdata, fw_sys_data_flags, 3616);
OFFSET_CHECK(struct rogue_fwif_sysdata, mc_config, 3620);
SIZE_CHECK(struct rogue_fwif_sysdata, 3624);
OFFSET_CHECK(struct rogue_fwif_slr_entry, timestamp, 0);
OFFSET_CHECK(struct rogue_fwif_slr_entry, fw_ctx_addr, 8);
OFFSET_CHECK(struct rogue_fwif_slr_entry, num_ufos, 12);
OFFSET_CHECK(struct rogue_fwif_slr_entry, ccb_name, 16);
SIZE_CHECK(struct rogue_fwif_slr_entry, 48);
OFFSET_CHECK(struct rogue_fwif_osdata, fw_os_config_flags, 0);
OFFSET_CHECK(struct rogue_fwif_osdata, fw_sync_check_mark, 4);
OFFSET_CHECK(struct rogue_fwif_osdata, host_sync_check_mark, 8);
OFFSET_CHECK(struct rogue_fwif_osdata, forced_updates_requested, 12);
OFFSET_CHECK(struct rogue_fwif_osdata, slr_log_wp, 16);
OFFSET_CHECK(struct rogue_fwif_osdata, slr_log_first, 24);
OFFSET_CHECK(struct rogue_fwif_osdata, slr_log, 72);
OFFSET_CHECK(struct rogue_fwif_osdata, last_forced_update_time, 552);
OFFSET_CHECK(struct rogue_fwif_osdata, interrupt_count, 560);
OFFSET_CHECK(struct rogue_fwif_osdata, kccb_cmds_executed, 568);
OFFSET_CHECK(struct rogue_fwif_osdata, power_sync_fw_addr, 572);
OFFSET_CHECK(struct rogue_fwif_osdata, fw_os_data_flags, 576);
SIZE_CHECK(struct rogue_fwif_osdata, 584);
OFFSET_CHECK(struct rogue_bifinfo, bif_req_status, 0);
OFFSET_CHECK(struct rogue_bifinfo, bif_mmu_status, 8);
OFFSET_CHECK(struct rogue_bifinfo, pc_address, 16);
OFFSET_CHECK(struct rogue_bifinfo, reserved, 24);
SIZE_CHECK(struct rogue_bifinfo, 32);
OFFSET_CHECK(struct rogue_eccinfo, fault_gpu, 0);
SIZE_CHECK(struct rogue_eccinfo, 4);
OFFSET_CHECK(struct rogue_mmuinfo, mmu_status, 0);
OFFSET_CHECK(struct rogue_mmuinfo, pc_address, 16);
OFFSET_CHECK(struct rogue_mmuinfo, reserved, 24);
SIZE_CHECK(struct rogue_mmuinfo, 32);
OFFSET_CHECK(struct rogue_pollinfo, thread_num, 0);
OFFSET_CHECK(struct rogue_pollinfo, cr_poll_addr, 4);
OFFSET_CHECK(struct rogue_pollinfo, cr_poll_mask, 8);
OFFSET_CHECK(struct rogue_pollinfo, cr_poll_last_value, 12);
OFFSET_CHECK(struct rogue_pollinfo, reserved, 16);
SIZE_CHECK(struct rogue_pollinfo, 24);
OFFSET_CHECK(struct rogue_tlbinfo, bad_addr, 0);
OFFSET_CHECK(struct rogue_tlbinfo, entry_lo, 4);
SIZE_CHECK(struct rogue_tlbinfo, 8);
OFFSET_CHECK(struct rogue_hwrinfo, hwr_data, 0);
OFFSET_CHECK(struct rogue_hwrinfo, cr_timer, 32);
OFFSET_CHECK(struct rogue_hwrinfo, os_timer, 40);
OFFSET_CHECK(struct rogue_hwrinfo, frame_num, 48);
OFFSET_CHECK(struct rogue_hwrinfo, pid, 52);
OFFSET_CHECK(struct rogue_hwrinfo, active_hwrt_data, 56);
OFFSET_CHECK(struct rogue_hwrinfo, hwr_number, 60);
OFFSET_CHECK(struct rogue_hwrinfo, event_status, 64);
OFFSET_CHECK(struct rogue_hwrinfo, hwr_recovery_flags, 68);
OFFSET_CHECK(struct rogue_hwrinfo, hwr_type, 72);
OFFSET_CHECK(struct rogue_hwrinfo, dm, 76);
OFFSET_CHECK(struct rogue_hwrinfo, core_id, 80);
OFFSET_CHECK(struct rogue_hwrinfo, cr_time_of_kick, 88);
OFFSET_CHECK(struct rogue_hwrinfo, cr_time_hw_reset_start, 96);
OFFSET_CHECK(struct rogue_hwrinfo, cr_time_hw_reset_finish, 104);
OFFSET_CHECK(struct rogue_hwrinfo, cr_time_freelist_ready, 112);
OFFSET_CHECK(struct rogue_hwrinfo, reserved, 120);
SIZE_CHECK(struct rogue_hwrinfo, 136);
OFFSET_CHECK(struct rogue_fwif_hwrinfobuf, hwr_info, 0);
OFFSET_CHECK(struct rogue_fwif_hwrinfobuf, hwr_counter, 2176);
OFFSET_CHECK(struct rogue_fwif_hwrinfobuf, write_index, 2180);
OFFSET_CHECK(struct rogue_fwif_hwrinfobuf, dd_req_count, 2184);
OFFSET_CHECK(struct rogue_fwif_hwrinfobuf, hwr_info_buf_flags, 2188);
OFFSET_CHECK(struct rogue_fwif_hwrinfobuf, hwr_dm_locked_up_count, 2192);
OFFSET_CHECK(struct rogue_fwif_hwrinfobuf, hwr_dm_overran_count, 2228);
OFFSET_CHECK(struct rogue_fwif_hwrinfobuf, hwr_dm_recovered_count, 2264);
OFFSET_CHECK(struct rogue_fwif_hwrinfobuf, hwr_dm_false_detect_count, 2300);
SIZE_CHECK(struct rogue_fwif_hwrinfobuf, 2336);
OFFSET_CHECK(struct rogue_fwif_fwmemcontext, pc_dev_paddr, 0);
OFFSET_CHECK(struct rogue_fwif_fwmemcontext, page_cat_base_reg_set, 8);
OFFSET_CHECK(struct rogue_fwif_fwmemcontext, breakpoint_addr, 12);
OFFSET_CHECK(struct rogue_fwif_fwmemcontext, bp_handler_addr, 16);
OFFSET_CHECK(struct rogue_fwif_fwmemcontext, breakpoint_ctl, 20);
OFFSET_CHECK(struct rogue_fwif_fwmemcontext, fw_mem_ctx_flags, 24);
SIZE_CHECK(struct rogue_fwif_fwmemcontext, 32);
OFFSET_CHECK(struct rogue_fwif_geom_ctx_state_per_geom, geom_reg_vdm_call_stack_pointer, 0);
OFFSET_CHECK(struct rogue_fwif_geom_ctx_state_per_geom, geom_reg_vdm_call_stack_pointer_init, 8);
OFFSET_CHECK(struct rogue_fwif_geom_ctx_state_per_geom, geom_reg_vbs_so_prim, 16);
OFFSET_CHECK(struct rogue_fwif_geom_ctx_state_per_geom, geom_current_idx, 32);
SIZE_CHECK(struct rogue_fwif_geom_ctx_state_per_geom, 40);
OFFSET_CHECK(struct rogue_fwif_geom_ctx_state, geom_core, 0);
SIZE_CHECK(struct rogue_fwif_geom_ctx_state, 160);
OFFSET_CHECK(struct rogue_fwif_frag_ctx_state, frag_reg_pm_deallocated_mask_status, 0);
OFFSET_CHECK(struct rogue_fwif_frag_ctx_state, frag_reg_dm_pds_mtilefree_status, 4);
OFFSET_CHECK(struct rogue_fwif_frag_ctx_state, ctx_state_flags, 8);
OFFSET_CHECK(struct rogue_fwif_frag_ctx_state, frag_reg_isp_store, 12);
SIZE_CHECK(struct rogue_fwif_frag_ctx_state, 16);
OFFSET_CHECK(struct rogue_fwif_compute_ctx_state, ctx_state_flags, 0);
SIZE_CHECK(struct rogue_fwif_compute_ctx_state, 4);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, ccbctl_fw_addr, 0);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, ccb_fw_addr, 4);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, ccb_meta_dma_addr, 8);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, context_state_addr, 24);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, fw_com_ctx_flags, 28);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, priority, 32);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, priority_seq_num, 36);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, rf_cmd_addr, 40);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, stats_pending, 44);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, stats_num_stores, 48);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, stats_num_out_of_memory, 52);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, stats_num_partial_renders, 56);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, dm, 60);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, wait_signal_address, 64);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, wait_signal_node, 72);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, buf_stalled_node, 80);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, cbuf_queue_ctrl_addr, 88);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, robustness_address, 96);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, max_deadline_ms, 104);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, read_offset_needs_reset, 108);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, waiting_node, 112);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, run_node, 120);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, last_failed_ufo, 128);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, fw_mem_context_fw_addr, 136);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, server_common_context_id, 140);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, pid, 144);
OFFSET_CHECK(struct rogue_fwif_fwcommoncontext, geom_oom_disabled, 148);
SIZE_CHECK(struct rogue_fwif_fwcommoncontext, 152);
OFFSET_CHECK(struct rogue_fwif_ccb_ctl, write_offset, 0);
OFFSET_CHECK(struct rogue_fwif_ccb_ctl, padding, 4);
OFFSET_CHECK(struct rogue_fwif_ccb_ctl, read_offset, 128);
OFFSET_CHECK(struct rogue_fwif_ccb_ctl, wrap_mask, 132);
OFFSET_CHECK(struct rogue_fwif_ccb_ctl, cmd_size, 136);
OFFSET_CHECK(struct rogue_fwif_ccb_ctl, padding2, 140);
SIZE_CHECK(struct rogue_fwif_ccb_ctl, 144);
OFFSET_CHECK(struct rogue_fwif_kccb_cmd_kick_data, context_fw_addr, 0);
OFFSET_CHECK(struct rogue_fwif_kccb_cmd_kick_data, client_woff_update, 4);
OFFSET_CHECK(struct rogue_fwif_kccb_cmd_kick_data, client_wrap_mask_update, 8);
OFFSET_CHECK(struct rogue_fwif_kccb_cmd_kick_data, num_cleanup_ctl, 12);
OFFSET_CHECK(struct rogue_fwif_kccb_cmd_kick_data, cleanup_ctl_fw_addr, 16);
OFFSET_CHECK(struct rogue_fwif_kccb_cmd_kick_data, work_est_cmd_header_offset, 28);
SIZE_CHECK(struct rogue_fwif_kccb_cmd_kick_data, 32);
OFFSET_CHECK(struct rogue_fwif_kccb_cmd_combined_geom_frag_kick_data, geom_cmd_kick_data, 0);
OFFSET_CHECK(struct rogue_fwif_kccb_cmd_combined_geom_frag_kick_data, frag_cmd_kick_data, 32);
SIZE_CHECK(struct rogue_fwif_kccb_cmd_combined_geom_frag_kick_data, 64);
OFFSET_CHECK(struct rogue_fwif_kccb_cmd_force_update_data, context_fw_addr, 0);
OFFSET_CHECK(struct rogue_fwif_kccb_cmd_force_update_data, ccb_fence_offset, 4);
SIZE_CHECK(struct rogue_fwif_kccb_cmd_force_update_data, 8);
OFFSET_CHECK(struct rogue_fwif_cleanup_request, cleanup_type, 0);
OFFSET_CHECK(struct rogue_fwif_cleanup_request, cleanup_data, 4);
SIZE_CHECK(struct rogue_fwif_cleanup_request, 8);
OFFSET_CHECK(struct rogue_fwif_power_request, pow_type, 0);
OFFSET_CHECK(struct rogue_fwif_power_request, power_req_data, 4);
SIZE_CHECK(struct rogue_fwif_power_request, 8);
OFFSET_CHECK(struct rogue_fwif_slcflushinvaldata, context_fw_addr, 0);
OFFSET_CHECK(struct rogue_fwif_slcflushinvaldata, inval, 4);
OFFSET_CHECK(struct rogue_fwif_slcflushinvaldata, dm_context, 8);
OFFSET_CHECK(struct rogue_fwif_slcflushinvaldata, address, 16);
OFFSET_CHECK(struct rogue_fwif_slcflushinvaldata, size, 24);
SIZE_CHECK(struct rogue_fwif_slcflushinvaldata, 32);
OFFSET_CHECK(struct rogue_fwif_hwperf_ctrl, opcode, 0);
OFFSET_CHECK(struct rogue_fwif_hwperf_ctrl, mask, 8);
SIZE_CHECK(struct rogue_fwif_hwperf_ctrl, 16);
OFFSET_CHECK(struct rogue_fwif_hwperf_config_enable_blks, num_blocks, 0);
OFFSET_CHECK(struct rogue_fwif_hwperf_config_enable_blks, block_configs_fw_addr, 4);
SIZE_CHECK(struct rogue_fwif_hwperf_config_enable_blks, 8);
OFFSET_CHECK(struct rogue_fwif_hwperf_config_da_blks, num_blocks, 0);
OFFSET_CHECK(struct rogue_fwif_hwperf_config_da_blks, block_configs_fw_addr, 4);
SIZE_CHECK(struct rogue_fwif_hwperf_config_da_blks, 8);
OFFSET_CHECK(struct rogue_fwif_coreclkspeedchange_data, new_clock_speed, 0);
SIZE_CHECK(struct rogue_fwif_coreclkspeedchange_data, 4);
OFFSET_CHECK(struct rogue_fwif_hwperf_ctrl_blks, enable, 0);
OFFSET_CHECK(struct rogue_fwif_hwperf_ctrl_blks, num_blocks, 4);
OFFSET_CHECK(struct rogue_fwif_hwperf_ctrl_blks, block_ids, 8);
SIZE_CHECK(struct rogue_fwif_hwperf_ctrl_blks, 40);
OFFSET_CHECK(struct rogue_fwif_hwperf_select_custom_cntrs, custom_block, 0);
OFFSET_CHECK(struct rogue_fwif_hwperf_select_custom_cntrs, num_counters, 2);
OFFSET_CHECK(struct rogue_fwif_hwperf_select_custom_cntrs, custom_counter_ids_fw_addr, 4);
SIZE_CHECK(struct rogue_fwif_hwperf_select_custom_cntrs, 8);
OFFSET_CHECK(struct rogue_fwif_zsbuffer_backing_data, zs_buffer_fw_addr, 0);
OFFSET_CHECK(struct rogue_fwif_zsbuffer_backing_data, done, 4);
SIZE_CHECK(struct rogue_fwif_zsbuffer_backing_data, 8);
OFFSET_CHECK(struct rogue_fwif_freelist_gs_data, freelist_fw_addr, 0);
OFFSET_CHECK(struct rogue_fwif_freelist_gs_data, delta_pages, 4);
OFFSET_CHECK(struct rogue_fwif_freelist_gs_data, new_pages, 8);
OFFSET_CHECK(struct rogue_fwif_freelist_gs_data, ready_pages, 12);
SIZE_CHECK(struct rogue_fwif_freelist_gs_data, 16);
OFFSET_CHECK(struct rogue_fwif_freelists_reconstruction_data, freelist_count, 0);
OFFSET_CHECK(struct rogue_fwif_freelists_reconstruction_data, freelist_ids, 4);
SIZE_CHECK(struct rogue_fwif_freelists_reconstruction_data, 76);
OFFSET_CHECK(struct rogue_fwif_write_offset_update_data, context_fw_addr, 0);
SIZE_CHECK(struct rogue_fwif_write_offset_update_data, 8);
OFFSET_CHECK(struct rogue_fwif_kccb_cmd, cmd_type, 0);
OFFSET_CHECK(struct rogue_fwif_kccb_cmd, kccb_flags, 4);
OFFSET_CHECK(struct rogue_fwif_kccb_cmd, cmd_data, 8);
SIZE_CHECK(struct rogue_fwif_kccb_cmd, 88);
OFFSET_CHECK(struct rogue_fwif_fwccb_cmd_context_reset_data, server_common_context_id, 0);
OFFSET_CHECK(struct rogue_fwif_fwccb_cmd_context_reset_data, reset_reason, 4);
OFFSET_CHECK(struct rogue_fwif_fwccb_cmd_context_reset_data, dm, 8);
OFFSET_CHECK(struct rogue_fwif_fwccb_cmd_context_reset_data, reset_job_ref, 12);
OFFSET_CHECK(struct rogue_fwif_fwccb_cmd_context_reset_data, flags, 16);
OFFSET_CHECK(struct rogue_fwif_fwccb_cmd_context_reset_data, pc_address, 24);
OFFSET_CHECK(struct rogue_fwif_fwccb_cmd_context_reset_data, fault_address, 32);
SIZE_CHECK(struct rogue_fwif_fwccb_cmd_context_reset_data, 40);
OFFSET_CHECK(struct rogue_fwif_fwccb_cmd_fw_pagefault_data, fw_fault_addr, 0);
SIZE_CHECK(struct rogue_fwif_fwccb_cmd_fw_pagefault_data, 8);
OFFSET_CHECK(struct rogue_fwif_fwccb_cmd, cmd_type, 0);
OFFSET_CHECK(struct rogue_fwif_fwccb_cmd, fwccb_flags, 4);
OFFSET_CHECK(struct rogue_fwif_fwccb_cmd, cmd_data, 8);
SIZE_CHECK(struct rogue_fwif_fwccb_cmd, 88);
OFFSET_CHECK(struct rogue_fwif_ccb_cmd_header, cmd_type, 0);
OFFSET_CHECK(struct rogue_fwif_ccb_cmd_header, cmd_size, 4);
OFFSET_CHECK(struct rogue_fwif_ccb_cmd_header, ext_job_ref, 8);
OFFSET_CHECK(struct rogue_fwif_ccb_cmd_header, int_job_ref, 12);
OFFSET_CHECK(struct rogue_fwif_ccb_cmd_header, work_est_kick_data, 16);
SIZE_CHECK(struct rogue_fwif_ccb_cmd_header, 40);
OFFSET_CHECK(struct rogue_fwif_runtime_cfg, active_pm_latency_ms, 0);
OFFSET_CHECK(struct rogue_fwif_runtime_cfg, runtime_cfg_flags, 4);
OFFSET_CHECK(struct rogue_fwif_runtime_cfg, active_pm_latency_persistant, 8);
OFFSET_CHECK(struct rogue_fwif_runtime_cfg, core_clock_speed, 12);
OFFSET_CHECK(struct rogue_fwif_runtime_cfg, default_dusts_num_init, 16);
OFFSET_CHECK(struct rogue_fwif_runtime_cfg, phr_mode, 20);
OFFSET_CHECK(struct rogue_fwif_runtime_cfg, hcs_deadline_ms, 24);
OFFSET_CHECK(struct rogue_fwif_runtime_cfg, wdg_period_us, 28);
OFFSET_CHECK(struct rogue_fwif_runtime_cfg, osid_priority, 32);
OFFSET_CHECK(struct rogue_fwif_runtime_cfg, hwperf_buf_fw_addr, 64);
OFFSET_CHECK(struct rogue_fwif_runtime_cfg, padding, 68);
SIZE_CHECK(struct rogue_fwif_runtime_cfg, 72);
OFFSET_CHECK(struct rogue_fwif_connection_ctl, connection_fw_state, 0);
OFFSET_CHECK(struct rogue_fwif_connection_ctl, connection_os_state, 4);
OFFSET_CHECK(struct rogue_fwif_connection_ctl, alive_fw_token, 8);
OFFSET_CHECK(struct rogue_fwif_connection_ctl, alive_os_token, 12);
SIZE_CHECK(struct rogue_fwif_connection_ctl, 16);
OFFSET_CHECK(struct rogue_fwif_compchecks_bvnc, layout_version, 0);
OFFSET_CHECK(struct rogue_fwif_compchecks_bvnc, bvnc, 8);
SIZE_CHECK(struct rogue_fwif_compchecks_bvnc, 16);
OFFSET_CHECK(struct rogue_fwif_init_options, os_count_support, 0);
SIZE_CHECK(struct rogue_fwif_init_options, 8);
OFFSET_CHECK(struct rogue_fwif_compchecks, hw_bvnc, 0);
OFFSET_CHECK(struct rogue_fwif_compchecks, fw_bvnc, 16);
OFFSET_CHECK(struct rogue_fwif_compchecks, fw_processor_version, 32);
OFFSET_CHECK(struct rogue_fwif_compchecks, ddk_version, 36);
OFFSET_CHECK(struct rogue_fwif_compchecks, ddk_build, 40);
OFFSET_CHECK(struct rogue_fwif_compchecks, build_options, 44);
OFFSET_CHECK(struct rogue_fwif_compchecks, init_options, 48);
OFFSET_CHECK(struct rogue_fwif_compchecks, updated, 56);
SIZE_CHECK(struct rogue_fwif_compchecks, 64);
OFFSET_CHECK(struct rogue_fwif_osinit, kernel_ccbctl_fw_addr, 0);
OFFSET_CHECK(struct rogue_fwif_osinit, kernel_ccb_fw_addr, 4);
OFFSET_CHECK(struct rogue_fwif_osinit, kernel_ccb_rtn_slots_fw_addr, 8);
OFFSET_CHECK(struct rogue_fwif_osinit, firmware_ccbctl_fw_addr, 12);
OFFSET_CHECK(struct rogue_fwif_osinit, firmware_ccb_fw_addr, 16);
OFFSET_CHECK(struct rogue_fwif_osinit, work_est_firmware_ccbctl_fw_addr, 20);
OFFSET_CHECK(struct rogue_fwif_osinit, work_est_firmware_ccb_fw_addr, 24);
OFFSET_CHECK(struct rogue_fwif_osinit, rogue_fwif_hwr_info_buf_ctl_fw_addr, 28);
OFFSET_CHECK(struct rogue_fwif_osinit, hwr_debug_dump_limit, 32);
OFFSET_CHECK(struct rogue_fwif_osinit, fw_os_data_fw_addr, 36);
OFFSET_CHECK(struct rogue_fwif_osinit, rogue_comp_checks, 40);
SIZE_CHECK(struct rogue_fwif_osinit, 104);
OFFSET_CHECK(struct rogue_fwif_sigbuf_ctl, buffer_fw_addr, 0);
OFFSET_CHECK(struct rogue_fwif_sigbuf_ctl, left_size_in_regs, 4);
SIZE_CHECK(struct rogue_fwif_sigbuf_ctl, 8);
OFFSET_CHECK(struct pdvfs_opp, volt, 0);
OFFSET_CHECK(struct pdvfs_opp, freq, 4);
SIZE_CHECK(struct pdvfs_opp, 8);
OFFSET_CHECK(struct rogue_fwif_pdvfs_opp, opp_values, 0);
OFFSET_CHECK(struct rogue_fwif_pdvfs_opp, min_opp_point, 128);
OFFSET_CHECK(struct rogue_fwif_pdvfs_opp, max_opp_point, 132);
SIZE_CHECK(struct rogue_fwif_pdvfs_opp, 136);
OFFSET_CHECK(struct rogue_fwif_counter_dump_ctl, buffer_fw_addr, 0);
OFFSET_CHECK(struct rogue_fwif_counter_dump_ctl, size_in_dwords, 4);
SIZE_CHECK(struct rogue_fwif_counter_dump_ctl, 8);
OFFSET_CHECK(struct rogue_hwperf_bvnc, bvnc_string, 0);
OFFSET_CHECK(struct rogue_hwperf_bvnc, bvnc_km_feature_flags, 24);
OFFSET_CHECK(struct rogue_hwperf_bvnc, num_bvnc_blocks, 28);
OFFSET_CHECK(struct rogue_hwperf_bvnc, bvnc_gpu_cores, 30);
OFFSET_CHECK(struct rogue_hwperf_bvnc, bvnc_blocks, 32);
SIZE_CHECK(struct rogue_hwperf_bvnc, 160);
OFFSET_CHECK(struct rogue_fwif_sysinit, fault_phys_addr, 0);
OFFSET_CHECK(struct rogue_fwif_sysinit, pds_exec_base, 8);
OFFSET_CHECK(struct rogue_fwif_sysinit, usc_exec_base, 16);
OFFSET_CHECK(struct rogue_fwif_sysinit, fbcdc_state_table_base, 24);
OFFSET_CHECK(struct rogue_fwif_sysinit, fbcdc_large_state_table_base, 32);
OFFSET_CHECK(struct rogue_fwif_sysinit, texture_heap_base, 40);
OFFSET_CHECK(struct rogue_fwif_sysinit, hw_perf_filter, 48);
OFFSET_CHECK(struct rogue_fwif_sysinit, slc3_fence_dev_addr, 56);
OFFSET_CHECK(struct rogue_fwif_sysinit, tpu_trilinear_frac_mask, 64);
OFFSET_CHECK(struct rogue_fwif_sysinit, sigbuf_ctl, 80);
OFFSET_CHECK(struct rogue_fwif_sysinit, pdvfs_opp_info, 152);
OFFSET_CHECK(struct rogue_fwif_sysinit, coremem_data_store, 288);
OFFSET_CHECK(struct rogue_fwif_sysinit, counter_dump_ctl, 304);
OFFSET_CHECK(struct rogue_fwif_sysinit, filter_flags, 312);
OFFSET_CHECK(struct rogue_fwif_sysinit, runtime_cfg_fw_addr, 316);
OFFSET_CHECK(struct rogue_fwif_sysinit, trace_buf_ctl_fw_addr, 320);
OFFSET_CHECK(struct rogue_fwif_sysinit, fw_sys_data_fw_addr, 324);
OFFSET_CHECK(struct rogue_fwif_sysinit, gpu_util_fw_cb_ctl_fw_addr, 328);
OFFSET_CHECK(struct rogue_fwif_sysinit, reg_cfg_fw_addr, 332);
OFFSET_CHECK(struct rogue_fwif_sysinit, hwperf_ctl_fw_addr, 336);
OFFSET_CHECK(struct rogue_fwif_sysinit, align_checks, 340);
OFFSET_CHECK(struct rogue_fwif_sysinit, initial_core_clock_speed, 344);
OFFSET_CHECK(struct rogue_fwif_sysinit, active_pm_latency_ms, 348);
OFFSET_CHECK(struct rogue_fwif_sysinit, firmware_started, 352);
OFFSET_CHECK(struct rogue_fwif_sysinit, marker_val, 356);
OFFSET_CHECK(struct rogue_fwif_sysinit, firmware_started_timestamp, 360);
OFFSET_CHECK(struct rogue_fwif_sysinit, jones_disable_mask, 364);
OFFSET_CHECK(struct rogue_fwif_sysinit, firmware_perf, 368);
OFFSET_CHECK(struct rogue_fwif_sysinit, core_clock_rate_fw_addr, 372);
OFFSET_CHECK(struct rogue_fwif_sysinit, gpio_validation_mode, 376);
OFFSET_CHECK(struct rogue_fwif_sysinit, bvnc_km_feature_flags, 380);
OFFSET_CHECK(struct rogue_fwif_sysinit, tfbc_compression_control, 540);
SIZE_CHECK(struct rogue_fwif_sysinit, 544);
OFFSET_CHECK(struct rogue_fwif_gpu_util_fwcb, time_corr, 0);
OFFSET_CHECK(struct rogue_fwif_gpu_util_fwcb, time_corr_seq_count, 10240);
OFFSET_CHECK(struct rogue_fwif_gpu_util_fwcb, gpu_util_flags, 10244);
OFFSET_CHECK(struct rogue_fwif_gpu_util_fwcb, last_word, 10248);
OFFSET_CHECK(struct rogue_fwif_gpu_util_fwcb, stats_counters, 10256);
SIZE_CHECK(struct rogue_fwif_gpu_util_fwcb, 10280);
OFFSET_CHECK(struct rogue_fwif_rta_ctl, render_target_index, 0);
OFFSET_CHECK(struct rogue_fwif_rta_ctl, current_render_target, 4);
OFFSET_CHECK(struct rogue_fwif_rta_ctl, active_render_targets, 8);
OFFSET_CHECK(struct rogue_fwif_rta_ctl, cumul_active_render_targets, 12);
OFFSET_CHECK(struct rogue_fwif_rta_ctl, valid_render_targets_fw_addr, 16);
OFFSET_CHECK(struct rogue_fwif_rta_ctl, rta_num_partial_renders_fw_addr, 20);
OFFSET_CHECK(struct rogue_fwif_rta_ctl, max_rts, 24);
OFFSET_CHECK(struct rogue_fwif_rta_ctl, rta_ctl_flags, 28);
SIZE_CHECK(struct rogue_fwif_rta_ctl, 32);
OFFSET_CHECK(struct rogue_fwif_freelist, freelist_dev_addr, 0);
OFFSET_CHECK(struct rogue_fwif_freelist, current_dev_addr, 8);
OFFSET_CHECK(struct rogue_fwif_freelist, current_stack_top, 16);
OFFSET_CHECK(struct rogue_fwif_freelist, max_pages, 20);
OFFSET_CHECK(struct rogue_fwif_freelist, grow_pages, 24);
OFFSET_CHECK(struct rogue_fwif_freelist, current_pages, 28);
OFFSET_CHECK(struct rogue_fwif_freelist, allocated_page_count, 32);
OFFSET_CHECK(struct rogue_fwif_freelist, allocated_mmu_page_count, 36);
OFFSET_CHECK(struct rogue_fwif_freelist, freelist_id, 40);
OFFSET_CHECK(struct rogue_fwif_freelist, grow_pending, 44);
OFFSET_CHECK(struct rogue_fwif_freelist, ready_pages, 48);
OFFSET_CHECK(struct rogue_fwif_freelist, freelist_flags, 52);
OFFSET_CHECK(struct rogue_fwif_freelist, pm_global_pb, 56);
SIZE_CHECK(struct rogue_fwif_freelist, 64);
OFFSET_CHECK(struct rogue_fwif_hwrtdata_common, geom_caches_need_zeroing, 0);
OFFSET_CHECK(struct rogue_fwif_hwrtdata_common, screen_pixel_max, 4);
OFFSET_CHECK(struct rogue_fwif_hwrtdata_common, multi_sample_ctl, 8);
OFFSET_CHECK(struct rogue_fwif_hwrtdata_common, flipped_multi_sample_ctl, 16);
OFFSET_CHECK(struct rogue_fwif_hwrtdata_common, tpc_stride, 24);
OFFSET_CHECK(struct rogue_fwif_hwrtdata_common, tpc_size, 28);
OFFSET_CHECK(struct rogue_fwif_hwrtdata_common, te_screen, 32);
OFFSET_CHECK(struct rogue_fwif_hwrtdata_common, mtile_stride, 36);
OFFSET_CHECK(struct rogue_fwif_hwrtdata_common, teaa, 40);
OFFSET_CHECK(struct rogue_fwif_hwrtdata_common, te_mtile1, 44);
OFFSET_CHECK(struct rogue_fwif_hwrtdata_common, te_mtile2, 48);
OFFSET_CHECK(struct rogue_fwif_hwrtdata_common, isp_merge_lower_x, 52);
OFFSET_CHECK(struct rogue_fwif_hwrtdata_common, isp_merge_lower_y, 56);
OFFSET_CHECK(struct rogue_fwif_hwrtdata_common, isp_merge_upper_x, 60);
OFFSET_CHECK(struct rogue_fwif_hwrtdata_common, isp_merge_upper_y, 64);
OFFSET_CHECK(struct rogue_fwif_hwrtdata_common, isp_merge_scale_x, 68);
OFFSET_CHECK(struct rogue_fwif_hwrtdata_common, isp_merge_scale_y, 72);
OFFSET_CHECK(struct rogue_fwif_hwrtdata_common, rgn_header_size, 76);
OFFSET_CHECK(struct rogue_fwif_hwrtdata_common, isp_mtile_size, 80);
SIZE_CHECK(struct rogue_fwif_hwrtdata_common, 88);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, pm_mlist_dev_addr, 0);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, vce_cat_base, 8);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, vce_last_cat_base, 40);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, te_cat_base, 72);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, te_last_cat_base, 104);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, alist_cat_base, 136);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, alist_last_cat_base, 144);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, pm_alist_stack_pointer, 152);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, pm_mlist_stack_pointer, 160);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, hwrt_data_common_fw_addr, 164);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, hwrt_data_flags, 168);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, state, 172);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, freelists_fw_addr, 176);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, freelist_hwr_snapshot, 188);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, vheap_table_dev_addr, 200);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, rta_ctl, 208);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, tail_ptrs_dev_addr, 240);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, macrotile_array_dev_addr, 248);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, rgn_header_dev_addr, 256);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, rtc_dev_addr, 264);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, owner_geom_not_used_by_host, 272);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, geom_caches_need_zeroing, 276);
OFFSET_CHECK(struct rogue_fwif_hwrtdata, cleanup_state, 320);
SIZE_CHECK(struct rogue_fwif_hwrtdata, 384);
OFFSET_CHECK(struct rogue_fwif_sync_checkpoint, state, 0);
OFFSET_CHECK(struct rogue_fwif_sync_checkpoint, fw_ref_count, 4);
SIZE_CHECK(struct rogue_fwif_sync_checkpoint, 8);
#endif /* PVR_ROGUE_FWIF_CHECK_H */

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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/* Copyright (c) 2023 Imagination Technologies Ltd. */
#ifndef PVR_ROGUE_FWIF_CLIENT_H
#define PVR_ROGUE_FWIF_CLIENT_H
#include <linux/bits.h>
#include <linux/kernel.h>
#include <linux/sizes.h>
#include <linux/types.h>
#include "pvr_rogue_fwif_shared.h"
/*
* Page size used for Parameter Management.
*/
#define ROGUE_PM_PAGE_SIZE SZ_4K
/*
* Minimum/Maximum PB size.
*
* Base page size is dependent on core:
* S6/S6XT/S7 = 50 pages
* S8XE = 40 pages
* S8XE with BRN66011 fixed = 25 pages
*
* Minimum PB = Base Pages + (NUM_TE_PIPES-1)*16K + (NUM_VCE_PIPES-1)*64K +
* IF_PM_PREALLOC(NUM_TE_PIPES*16K + NUM_VCE_PIPES*16K)
*
* Maximum PB size must ensure that no PM address space can be fully used,
* because if the full address space was used it would wrap and corrupt itself.
* Since there are two freelists (local is always minimum sized) this can be
* described as following three conditions being met:
*
* (Minimum PB + Maximum PB) < ALIST PM address space size (16GB)
* (Minimum PB + Maximum PB) < TE PM address space size (16GB) / NUM_TE_PIPES
* (Minimum PB + Maximum PB) < VCE PM address space size (16GB) / NUM_VCE_PIPES
*
* Since the max of NUM_TE_PIPES and NUM_VCE_PIPES is 4, we have a hard limit
* of 4GB minus the Minimum PB. For convenience we take the smaller power-of-2
* value of 2GB. This is far more than any current applications use.
*/
#define ROGUE_PM_MAX_FREELIST_SIZE SZ_2G
/*
* Flags supported by the geometry DM command i.e. &struct rogue_fwif_cmd_geom.
*/
#define ROGUE_GEOM_FLAGS_FIRSTKICK BIT_MASK(0)
#define ROGUE_GEOM_FLAGS_LASTKICK BIT_MASK(1)
/* Use single core in a multi core setup. */
#define ROGUE_GEOM_FLAGS_SINGLE_CORE BIT_MASK(3)
/*
* Flags supported by the fragment DM command i.e. &struct rogue_fwif_cmd_frag.
*/
/* Use single core in a multi core setup. */
#define ROGUE_FRAG_FLAGS_SINGLE_CORE BIT_MASK(3)
/* Indicates whether this render produces visibility results. */
#define ROGUE_FRAG_FLAGS_GET_VIS_RESULTS BIT_MASK(5)
/* Indicates whether a depth buffer is present. */
#define ROGUE_FRAG_FLAGS_DEPTHBUFFER BIT_MASK(7)
/* Indicates whether a stencil buffer is present. */
#define ROGUE_FRAG_FLAGS_STENCILBUFFER BIT_MASK(8)
/* Disable pixel merging for this render. */
#define ROGUE_FRAG_FLAGS_DISABLE_PIXELMERGE BIT_MASK(15)
/* Indicates whether a scratch buffer is present. */
#define ROGUE_FRAG_FLAGS_SCRATCHBUFFER BIT_MASK(19)
/* Disallow compute overlapped with this render. */
#define ROGUE_FRAG_FLAGS_PREVENT_CDM_OVERLAP BIT_MASK(26)
/*
* Flags supported by the compute DM command i.e. &struct rogue_fwif_cmd_compute.
*/
#define ROGUE_COMPUTE_FLAG_PREVENT_ALL_OVERLAP BIT_MASK(2)
/*!< Use single core in a multi core setup. */
#define ROGUE_COMPUTE_FLAG_SINGLE_CORE BIT_MASK(5)
/*
* Flags supported by the transfer DM command i.e. &struct rogue_fwif_cmd_transfer.
*/
/*!< Use single core in a multi core setup. */
#define ROGUE_TRANSFER_FLAGS_SINGLE_CORE BIT_MASK(1)
/*
************************************************
* Parameter/HWRTData control structures.
************************************************
*/
/*
* Configuration registers which need to be loaded by the firmware before a geometry
* job can be started.
*/
struct rogue_fwif_geom_regs {
u64 vdm_ctrl_stream_base;
u64 tpu_border_colour_table;
/* Only used when feature VDM_DRAWINDIRECT present. */
u64 vdm_draw_indirect0;
/* Only used when feature VDM_DRAWINDIRECT present. */
u32 vdm_draw_indirect1;
u32 ppp_ctrl;
u32 te_psg;
/* Only used when BRN 49927 present. */
u32 tpu;
u32 vdm_context_resume_task0_size;
/* Only used when feature VDM_OBJECT_LEVEL_LLS present. */
u32 vdm_context_resume_task3_size;
/* Only used when BRN 56279 or BRN 67381 present. */
u32 pds_ctrl;
u32 view_idx;
/* Only used when feature TESSELLATION present */
u32 pds_coeff_free_prog;
u32 padding;
};
/* Only used when BRN 44455 or BRN 63027 present. */
struct rogue_fwif_dummy_rgnhdr_init_geom_regs {
u64 te_psgregion_addr;
};
/*
* Represents a geometry command that can be used to tile a whole scene's objects as
* per TA behavior.
*/
struct rogue_fwif_cmd_geom {
/*
* rogue_fwif_cmd_geom_frag_shared field must always be at the beginning of the
* struct.
*
* The command struct (rogue_fwif_cmd_geom) is shared between Client and
* Firmware. Kernel is unable to perform read/write operations on the
* command struct, the SHARED region is the only exception from this rule.
* This region must be the first member so that Kernel can easily access it.
* For more info, see rogue_fwif_cmd_geom_frag_shared definition.
*/
struct rogue_fwif_cmd_geom_frag_shared cmd_shared;
struct rogue_fwif_geom_regs regs __aligned(8);
u32 flags __aligned(8);
/*
* Holds the geometry/fragment fence value to allow the fragment partial render command
* to go through.
*/
struct rogue_fwif_ufo partial_render_geom_frag_fence;
/* Only used when BRN 44455 or BRN 63027 present. */
struct rogue_fwif_dummy_rgnhdr_init_geom_regs dummy_rgnhdr_init_geom_regs __aligned(8);
/* Only used when BRN 61484 or BRN 66333 present. */
u32 brn61484_66333_live_rt;
u32 padding;
};
/*
* Configuration registers which need to be loaded by the firmware before ISP
* can be started.
*/
struct rogue_fwif_frag_regs {
u32 usc_pixel_output_ctrl;
#define ROGUE_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL 8U
u32 usc_clear_register[ROGUE_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL];
u32 isp_bgobjdepth;
u32 isp_bgobjvals;
u32 isp_aa;
/* Only used when feature S7_TOP_INFRASTRUCTURE present. */
u32 isp_xtp_pipe_enable;
u32 isp_ctl;
/* Only used when BRN 49927 present. */
u32 tpu;
u32 event_pixel_pds_info;
/* Only used when feature CLUSTER_GROUPING present. */
u32 pixel_phantom;
u32 view_idx;
u32 event_pixel_pds_data;
/* Only used when BRN 65101 present. */
u32 brn65101_event_pixel_pds_data;
/* Only used when feature GPU_MULTICORE_SUPPORT or BRN 47217 present. */
u32 isp_oclqry_stride;
/* Only used when feature ZLS_SUBTILE present. */
u32 isp_zls_pixels;
/* Only used when feature ISP_ZLS_D24_S8_PACKING_OGL_MODE present. */
u32 rgx_cr_blackpearl_fix;
/* All values below the ALIGN(8) must be 64 bit. */
aligned_u64 isp_scissor_base;
u64 isp_dbias_base;
u64 isp_oclqry_base;
u64 isp_zlsctl;
u64 isp_zload_store_base;
u64 isp_stencil_load_store_base;
/*
* Only used when feature FBCDC_ALGORITHM present and value < 3 or feature
* FB_CDC_V4 present. Additionally, BRNs 48754, 60227, 72310 and 72311 must
* not be present.
*/
u64 fb_cdc_zls;
#define ROGUE_PBE_WORDS_REQUIRED_FOR_RENDERS 3U
u64 pbe_word[8U][ROGUE_PBE_WORDS_REQUIRED_FOR_RENDERS];
u64 tpu_border_colour_table;
u64 pds_bgnd[3U];
/* Only used when BRN 65101 present. */
u64 pds_bgnd_brn65101[3U];
u64 pds_pr_bgnd[3U];
/* Only used when BRN 62850 or 62865 present. */
u64 isp_dummy_stencil_store_base;
/* Only used when BRN 66193 present. */
u64 isp_dummy_depth_store_base;
/* Only used when BRN 67182 present. */
u32 rgnhdr_single_rt_size;
/* Only used when BRN 67182 present. */
u32 rgnhdr_scratch_offset;
};
struct rogue_fwif_cmd_frag {
struct rogue_fwif_cmd_geom_frag_shared cmd_shared __aligned(8);
struct rogue_fwif_frag_regs regs __aligned(8);
/* command control flags. */
u32 flags;
/* Stride IN BYTES for Z-Buffer in case of RTAs. */
u32 zls_stride;
/* Stride IN BYTES for S-Buffer in case of RTAs. */
u32 sls_stride;
/* Only used if feature GPU_MULTICORE_SUPPORT present. */
u32 execute_count;
};
/*
* Configuration registers which need to be loaded by the firmware before CDM
* can be started.
*/
struct rogue_fwif_compute_regs {
u64 tpu_border_colour_table;
/* Only used when feature CDM_USER_MODE_QUEUE present. */
u64 cdm_cb_queue;
/* Only used when feature CDM_USER_MODE_QUEUE present. */
u64 cdm_cb_base;
/* Only used when feature CDM_USER_MODE_QUEUE present. */
u64 cdm_cb;
/* Only used when feature CDM_USER_MODE_QUEUE is not present. */
u64 cdm_ctrl_stream_base;
u64 cdm_context_state_base_addr;
/* Only used when BRN 49927 is present. */
u32 tpu;
u32 cdm_resume_pds1;
/* Only used when feature COMPUTE_MORTON_CAPABLE present. */
u32 cdm_item;
/* Only used when feature CLUSTER_GROUPING present. */
u32 compute_cluster;
/* Only used when feature TPU_DM_GLOBAL_REGISTERS present. */
u32 tpu_tag_cdm_ctrl;
u32 padding;
};
struct rogue_fwif_cmd_compute {
/* Common command attributes */
struct rogue_fwif_cmd_common common __aligned(8);
/* CDM registers */
struct rogue_fwif_compute_regs regs;
/* Control flags */
u32 flags __aligned(8);
/* Only used when feature UNIFIED_STORE_VIRTUAL_PARTITIONING present. */
u32 num_temp_regions;
/* Only used when feature CDM_USER_MODE_QUEUE present. */
u32 stream_start_offset;
/* Only used when feature GPU_MULTICORE_SUPPORT present. */
u32 execute_count;
};
struct rogue_fwif_transfer_regs {
/*
* All 32 bit values should be added in the top section. This then requires only a
* single RGXFW_ALIGN to align all the 64 bit values in the second section.
*/
u32 isp_bgobjvals;
u32 usc_pixel_output_ctrl;
u32 usc_clear_register0;
u32 usc_clear_register1;
u32 usc_clear_register2;
u32 usc_clear_register3;
u32 isp_mtile_size;
u32 isp_render_origin;
u32 isp_ctl;
/* Only used when feature S7_TOP_INFRASTRUCTURE present. */
u32 isp_xtp_pipe_enable;
u32 isp_aa;
u32 event_pixel_pds_info;
u32 event_pixel_pds_code;
u32 event_pixel_pds_data;
u32 isp_render;
u32 isp_rgn;
/* Only used when feature GPU_MULTICORE_SUPPORT present. */
u32 frag_screen;
/* All values below the aligned_u64 must be 64 bit. */
aligned_u64 pds_bgnd0_base;
u64 pds_bgnd1_base;
u64 pds_bgnd3_sizeinfo;
u64 isp_mtile_base;
#define ROGUE_PBE_WORDS_REQUIRED_FOR_TQS 3
/* TQ_MAX_RENDER_TARGETS * PBE_STATE_SIZE */
u64 pbe_wordx_mrty[3U * ROGUE_PBE_WORDS_REQUIRED_FOR_TQS];
};
struct rogue_fwif_cmd_transfer {
/* Common command attributes */
struct rogue_fwif_cmd_common common __aligned(8);
struct rogue_fwif_transfer_regs regs __aligned(8);
u32 flags;
u32 padding;
};
#include "pvr_rogue_fwif_client_check.h"
#endif /* PVR_ROGUE_FWIF_CLIENT_H */

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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/* Copyright (c) 2023 Imagination Technologies Ltd. */
#ifndef PVR_ROGUE_FWIF_CLIENT_CHECK_H
#define PVR_ROGUE_FWIF_CLIENT_CHECK_H
#include <linux/build_bug.h>
#define OFFSET_CHECK(type, member, offset) \
static_assert(offsetof(type, member) == (offset), \
"offsetof(" #type ", " #member ") incorrect")
#define SIZE_CHECK(type, size) \
static_assert(sizeof(type) == (size), #type " is incorrect size")
OFFSET_CHECK(struct rogue_fwif_geom_regs, vdm_ctrl_stream_base, 0);
OFFSET_CHECK(struct rogue_fwif_geom_regs, tpu_border_colour_table, 8);
OFFSET_CHECK(struct rogue_fwif_geom_regs, vdm_draw_indirect0, 16);
OFFSET_CHECK(struct rogue_fwif_geom_regs, vdm_draw_indirect1, 24);
OFFSET_CHECK(struct rogue_fwif_geom_regs, ppp_ctrl, 28);
OFFSET_CHECK(struct rogue_fwif_geom_regs, te_psg, 32);
OFFSET_CHECK(struct rogue_fwif_geom_regs, tpu, 36);
OFFSET_CHECK(struct rogue_fwif_geom_regs, vdm_context_resume_task0_size, 40);
OFFSET_CHECK(struct rogue_fwif_geom_regs, vdm_context_resume_task3_size, 44);
OFFSET_CHECK(struct rogue_fwif_geom_regs, pds_ctrl, 48);
OFFSET_CHECK(struct rogue_fwif_geom_regs, view_idx, 52);
OFFSET_CHECK(struct rogue_fwif_geom_regs, pds_coeff_free_prog, 56);
SIZE_CHECK(struct rogue_fwif_geom_regs, 64);
OFFSET_CHECK(struct rogue_fwif_dummy_rgnhdr_init_geom_regs, te_psgregion_addr, 0);
SIZE_CHECK(struct rogue_fwif_dummy_rgnhdr_init_geom_regs, 8);
OFFSET_CHECK(struct rogue_fwif_cmd_geom, cmd_shared, 0);
OFFSET_CHECK(struct rogue_fwif_cmd_geom, regs, 16);
OFFSET_CHECK(struct rogue_fwif_cmd_geom, flags, 80);
OFFSET_CHECK(struct rogue_fwif_cmd_geom, partial_render_geom_frag_fence, 84);
OFFSET_CHECK(struct rogue_fwif_cmd_geom, dummy_rgnhdr_init_geom_regs, 96);
OFFSET_CHECK(struct rogue_fwif_cmd_geom, brn61484_66333_live_rt, 104);
SIZE_CHECK(struct rogue_fwif_cmd_geom, 112);
OFFSET_CHECK(struct rogue_fwif_frag_regs, usc_pixel_output_ctrl, 0);
OFFSET_CHECK(struct rogue_fwif_frag_regs, usc_clear_register, 4);
OFFSET_CHECK(struct rogue_fwif_frag_regs, isp_bgobjdepth, 36);
OFFSET_CHECK(struct rogue_fwif_frag_regs, isp_bgobjvals, 40);
OFFSET_CHECK(struct rogue_fwif_frag_regs, isp_aa, 44);
OFFSET_CHECK(struct rogue_fwif_frag_regs, isp_xtp_pipe_enable, 48);
OFFSET_CHECK(struct rogue_fwif_frag_regs, isp_ctl, 52);
OFFSET_CHECK(struct rogue_fwif_frag_regs, tpu, 56);
OFFSET_CHECK(struct rogue_fwif_frag_regs, event_pixel_pds_info, 60);
OFFSET_CHECK(struct rogue_fwif_frag_regs, pixel_phantom, 64);
OFFSET_CHECK(struct rogue_fwif_frag_regs, view_idx, 68);
OFFSET_CHECK(struct rogue_fwif_frag_regs, event_pixel_pds_data, 72);
OFFSET_CHECK(struct rogue_fwif_frag_regs, brn65101_event_pixel_pds_data, 76);
OFFSET_CHECK(struct rogue_fwif_frag_regs, isp_oclqry_stride, 80);
OFFSET_CHECK(struct rogue_fwif_frag_regs, isp_zls_pixels, 84);
OFFSET_CHECK(struct rogue_fwif_frag_regs, rgx_cr_blackpearl_fix, 88);
OFFSET_CHECK(struct rogue_fwif_frag_regs, isp_scissor_base, 96);
OFFSET_CHECK(struct rogue_fwif_frag_regs, isp_dbias_base, 104);
OFFSET_CHECK(struct rogue_fwif_frag_regs, isp_oclqry_base, 112);
OFFSET_CHECK(struct rogue_fwif_frag_regs, isp_zlsctl, 120);
OFFSET_CHECK(struct rogue_fwif_frag_regs, isp_zload_store_base, 128);
OFFSET_CHECK(struct rogue_fwif_frag_regs, isp_stencil_load_store_base, 136);
OFFSET_CHECK(struct rogue_fwif_frag_regs, fb_cdc_zls, 144);
OFFSET_CHECK(struct rogue_fwif_frag_regs, pbe_word, 152);
OFFSET_CHECK(struct rogue_fwif_frag_regs, tpu_border_colour_table, 344);
OFFSET_CHECK(struct rogue_fwif_frag_regs, pds_bgnd, 352);
OFFSET_CHECK(struct rogue_fwif_frag_regs, pds_bgnd_brn65101, 376);
OFFSET_CHECK(struct rogue_fwif_frag_regs, pds_pr_bgnd, 400);
OFFSET_CHECK(struct rogue_fwif_frag_regs, isp_dummy_stencil_store_base, 424);
OFFSET_CHECK(struct rogue_fwif_frag_regs, isp_dummy_depth_store_base, 432);
OFFSET_CHECK(struct rogue_fwif_frag_regs, rgnhdr_single_rt_size, 440);
OFFSET_CHECK(struct rogue_fwif_frag_regs, rgnhdr_scratch_offset, 444);
SIZE_CHECK(struct rogue_fwif_frag_regs, 448);
OFFSET_CHECK(struct rogue_fwif_cmd_frag, cmd_shared, 0);
OFFSET_CHECK(struct rogue_fwif_cmd_frag, regs, 16);
OFFSET_CHECK(struct rogue_fwif_cmd_frag, flags, 464);
OFFSET_CHECK(struct rogue_fwif_cmd_frag, zls_stride, 468);
OFFSET_CHECK(struct rogue_fwif_cmd_frag, sls_stride, 472);
OFFSET_CHECK(struct rogue_fwif_cmd_frag, execute_count, 476);
SIZE_CHECK(struct rogue_fwif_cmd_frag, 480);
OFFSET_CHECK(struct rogue_fwif_compute_regs, tpu_border_colour_table, 0);
OFFSET_CHECK(struct rogue_fwif_compute_regs, cdm_cb_queue, 8);
OFFSET_CHECK(struct rogue_fwif_compute_regs, cdm_cb_base, 16);
OFFSET_CHECK(struct rogue_fwif_compute_regs, cdm_cb, 24);
OFFSET_CHECK(struct rogue_fwif_compute_regs, cdm_ctrl_stream_base, 32);
OFFSET_CHECK(struct rogue_fwif_compute_regs, cdm_context_state_base_addr, 40);
OFFSET_CHECK(struct rogue_fwif_compute_regs, tpu, 48);
OFFSET_CHECK(struct rogue_fwif_compute_regs, cdm_resume_pds1, 52);
OFFSET_CHECK(struct rogue_fwif_compute_regs, cdm_item, 56);
OFFSET_CHECK(struct rogue_fwif_compute_regs, compute_cluster, 60);
OFFSET_CHECK(struct rogue_fwif_compute_regs, tpu_tag_cdm_ctrl, 64);
SIZE_CHECK(struct rogue_fwif_compute_regs, 72);
OFFSET_CHECK(struct rogue_fwif_cmd_compute, common, 0);
OFFSET_CHECK(struct rogue_fwif_cmd_compute, regs, 8);
OFFSET_CHECK(struct rogue_fwif_cmd_compute, flags, 80);
OFFSET_CHECK(struct rogue_fwif_cmd_compute, num_temp_regions, 84);
OFFSET_CHECK(struct rogue_fwif_cmd_compute, stream_start_offset, 88);
OFFSET_CHECK(struct rogue_fwif_cmd_compute, execute_count, 92);
SIZE_CHECK(struct rogue_fwif_cmd_compute, 96);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, isp_bgobjvals, 0);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, usc_pixel_output_ctrl, 4);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, usc_clear_register0, 8);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, usc_clear_register1, 12);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, usc_clear_register2, 16);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, usc_clear_register3, 20);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, isp_mtile_size, 24);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, isp_render_origin, 28);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, isp_ctl, 32);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, isp_xtp_pipe_enable, 36);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, isp_aa, 40);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, event_pixel_pds_info, 44);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, event_pixel_pds_code, 48);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, event_pixel_pds_data, 52);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, isp_render, 56);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, isp_rgn, 60);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, frag_screen, 64);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, pds_bgnd0_base, 72);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, pds_bgnd1_base, 80);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, pds_bgnd3_sizeinfo, 88);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, isp_mtile_base, 96);
OFFSET_CHECK(struct rogue_fwif_transfer_regs, pbe_wordx_mrty, 104);
SIZE_CHECK(struct rogue_fwif_transfer_regs, 176);
OFFSET_CHECK(struct rogue_fwif_cmd_transfer, common, 0);
OFFSET_CHECK(struct rogue_fwif_cmd_transfer, regs, 8);
OFFSET_CHECK(struct rogue_fwif_cmd_transfer, flags, 184);
SIZE_CHECK(struct rogue_fwif_cmd_transfer, 192);
#endif /* PVR_ROGUE_FWIF_CLIENT_CHECK_H */

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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/* Copyright (c) 2023 Imagination Technologies Ltd. */
#ifndef PVR_ROGUE_FWIF_COMMON_H
#define PVR_ROGUE_FWIF_COMMON_H
#include <linux/build_bug.h>
/*
* This macro represents a mask of LSBs that must be zero on data structure
* sizes and offsets to ensure they are 8-byte granular on types shared between
* the FW and host driver.
*/
#define PVR_FW_ALIGNMENT_LSB 7U
/* Macro to test structure size alignment. */
#define PVR_FW_STRUCT_SIZE_ASSERT(_a) \
static_assert((sizeof(_a) & PVR_FW_ALIGNMENT_LSB) == 0U, \
"Size of " #_a " is not properly aligned")
/* The master definition for data masters known to the firmware. */
#define PVR_FWIF_DM_GP (0)
/* Either TDM or 2D DM is present. */
/* When the 'tla' feature is present in the hw (as per @pvr_device_features). */
#define PVR_FWIF_DM_2D (1)
/*
* When the 'fastrender_dm' feature is present in the hw (as per
* @pvr_device_features).
*/
#define PVR_FWIF_DM_TDM (1)
#define PVR_FWIF_DM_GEOM (2)
#define PVR_FWIF_DM_FRAG (3)
#define PVR_FWIF_DM_CDM (4)
#define PVR_FWIF_DM_RAY (5)
#define PVR_FWIF_DM_GEOM2 (6)
#define PVR_FWIF_DM_GEOM3 (7)
#define PVR_FWIF_DM_GEOM4 (8)
#define PVR_FWIF_DM_LAST PVR_FWIF_DM_GEOM4
/* Maximum number of DM in use: GP, 2D/TDM, GEOM, 3D, CDM, RAY, GEOM2, GEOM3, GEOM4 */
#define PVR_FWIF_DM_MAX (PVR_FWIF_DM_LAST + 1U)
/* GPU Utilisation states */
#define PVR_FWIF_GPU_UTIL_STATE_IDLE 0U
#define PVR_FWIF_GPU_UTIL_STATE_ACTIVE 1U
#define PVR_FWIF_GPU_UTIL_STATE_BLOCKED 2U
#define PVR_FWIF_GPU_UTIL_STATE_NUM 3U
#define PVR_FWIF_GPU_UTIL_STATE_MASK 0x3ULL
/*
* Maximum amount of register writes that can be done by the register
* programmer (FW or META DMA). This is not a HW limitation, it is only
* a protection against malformed inputs to the register programmer.
*/
#define PVR_MAX_NUM_REGISTER_PROGRAMMER_WRITES 128U
#endif /* PVR_ROGUE_FWIF_COMMON_H */

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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/* Copyright (c) 2023 Imagination Technologies Ltd. */
#ifndef __PVR_ROGUE_FWIF_DEV_INFO_H__
#define __PVR_ROGUE_FWIF_DEV_INFO_H__
enum {
PVR_FW_HAS_BRN_44079 = 0,
PVR_FW_HAS_BRN_47217,
PVR_FW_HAS_BRN_48492,
PVR_FW_HAS_BRN_48545,
PVR_FW_HAS_BRN_49927,
PVR_FW_HAS_BRN_50767,
PVR_FW_HAS_BRN_51764,
PVR_FW_HAS_BRN_62269,
PVR_FW_HAS_BRN_63142,
PVR_FW_HAS_BRN_63553,
PVR_FW_HAS_BRN_66011,
PVR_FW_HAS_BRN_71242,
PVR_FW_HAS_BRN_MAX
};
enum {
PVR_FW_HAS_ERN_35421 = 0,
PVR_FW_HAS_ERN_38020,
PVR_FW_HAS_ERN_38748,
PVR_FW_HAS_ERN_42064,
PVR_FW_HAS_ERN_42290,
PVR_FW_HAS_ERN_42606,
PVR_FW_HAS_ERN_47025,
PVR_FW_HAS_ERN_57596,
PVR_FW_HAS_ERN_MAX
};
enum {
PVR_FW_HAS_FEATURE_AXI_ACELITE = 0,
PVR_FW_HAS_FEATURE_CDM_CONTROL_STREAM_FORMAT,
PVR_FW_HAS_FEATURE_CLUSTER_GROUPING,
PVR_FW_HAS_FEATURE_COMMON_STORE_SIZE_IN_DWORDS,
PVR_FW_HAS_FEATURE_COMPUTE,
PVR_FW_HAS_FEATURE_COMPUTE_MORTON_CAPABLE,
PVR_FW_HAS_FEATURE_COMPUTE_OVERLAP,
PVR_FW_HAS_FEATURE_COREID_PER_OS,
PVR_FW_HAS_FEATURE_DYNAMIC_DUST_POWER,
PVR_FW_HAS_FEATURE_ECC_RAMS,
PVR_FW_HAS_FEATURE_FBCDC,
PVR_FW_HAS_FEATURE_FBCDC_ALGORITHM,
PVR_FW_HAS_FEATURE_FBCDC_ARCHITECTURE,
PVR_FW_HAS_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS,
PVR_FW_HAS_FEATURE_FBC_MAX_LARGE_DESCRIPTORS,
PVR_FW_HAS_FEATURE_FB_CDC_V4,
PVR_FW_HAS_FEATURE_GPU_MULTICORE_SUPPORT,
PVR_FW_HAS_FEATURE_GPU_VIRTUALISATION,
PVR_FW_HAS_FEATURE_GS_RTA_SUPPORT,
PVR_FW_HAS_FEATURE_IRQ_PER_OS,
PVR_FW_HAS_FEATURE_ISP_MAX_TILES_IN_FLIGHT,
PVR_FW_HAS_FEATURE_ISP_SAMPLES_PER_PIXEL,
PVR_FW_HAS_FEATURE_ISP_ZLS_D24_S8_PACKING_OGL_MODE,
PVR_FW_HAS_FEATURE_LAYOUT_MARS,
PVR_FW_HAS_FEATURE_MAX_PARTITIONS,
PVR_FW_HAS_FEATURE_META,
PVR_FW_HAS_FEATURE_META_COREMEM_SIZE,
PVR_FW_HAS_FEATURE_MIPS,
PVR_FW_HAS_FEATURE_NUM_CLUSTERS,
PVR_FW_HAS_FEATURE_NUM_ISP_IPP_PIPES,
PVR_FW_HAS_FEATURE_NUM_OSIDS,
PVR_FW_HAS_FEATURE_NUM_RASTER_PIPES,
PVR_FW_HAS_FEATURE_PBE2_IN_XE,
PVR_FW_HAS_FEATURE_PBVNC_COREID_REG,
PVR_FW_HAS_FEATURE_PERFBUS,
PVR_FW_HAS_FEATURE_PERF_COUNTER_BATCH,
PVR_FW_HAS_FEATURE_PHYS_BUS_WIDTH,
PVR_FW_HAS_FEATURE_RISCV_FW_PROCESSOR,
PVR_FW_HAS_FEATURE_ROGUEXE,
PVR_FW_HAS_FEATURE_S7_TOP_INFRASTRUCTURE,
PVR_FW_HAS_FEATURE_SIMPLE_INTERNAL_PARAMETER_FORMAT,
PVR_FW_HAS_FEATURE_SIMPLE_INTERNAL_PARAMETER_FORMAT_V2,
PVR_FW_HAS_FEATURE_SIMPLE_PARAMETER_FORMAT_VERSION,
PVR_FW_HAS_FEATURE_SLC_BANKS,
PVR_FW_HAS_FEATURE_SLC_CACHE_LINE_SIZE_BITS,
PVR_FW_HAS_FEATURE_SLC_SIZE_CONFIGURABLE,
PVR_FW_HAS_FEATURE_SLC_SIZE_IN_KILOBYTES,
PVR_FW_HAS_FEATURE_SOC_TIMER,
PVR_FW_HAS_FEATURE_SYS_BUS_SECURE_RESET,
PVR_FW_HAS_FEATURE_TESSELLATION,
PVR_FW_HAS_FEATURE_TILE_REGION_PROTECTION,
PVR_FW_HAS_FEATURE_TILE_SIZE_X,
PVR_FW_HAS_FEATURE_TILE_SIZE_Y,
PVR_FW_HAS_FEATURE_TLA,
PVR_FW_HAS_FEATURE_TPU_CEM_DATAMASTER_GLOBAL_REGISTERS,
PVR_FW_HAS_FEATURE_TPU_DM_GLOBAL_REGISTERS,
PVR_FW_HAS_FEATURE_TPU_FILTERING_MODE_CONTROL,
PVR_FW_HAS_FEATURE_USC_MIN_OUTPUT_REGISTERS_PER_PIX,
PVR_FW_HAS_FEATURE_VDM_DRAWINDIRECT,
PVR_FW_HAS_FEATURE_VDM_OBJECT_LEVEL_LLS,
PVR_FW_HAS_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS,
PVR_FW_HAS_FEATURE_WATCHDOG_TIMER,
PVR_FW_HAS_FEATURE_WORKGROUP_PROTECTION,
PVR_FW_HAS_FEATURE_XE_ARCHITECTURE,
PVR_FW_HAS_FEATURE_XE_MEMORY_HIERARCHY,
PVR_FW_HAS_FEATURE_XE_TPU2,
PVR_FW_HAS_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH,
PVR_FW_HAS_FEATURE_XPU_MAX_SLAVES,
PVR_FW_HAS_FEATURE_XPU_REGISTER_BROADCAST,
PVR_FW_HAS_FEATURE_XT_TOP_INFRASTRUCTURE,
PVR_FW_HAS_FEATURE_ZLS_SUBTILE,
PVR_FW_HAS_FEATURE_MAX
};
#endif /* __PVR_ROGUE_FWIF_DEV_INFO_H__ */

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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/* Copyright (c) 2023 Imagination Technologies Ltd. */
#ifndef PVR_ROGUE_FWIF_RESETFRAMEWORK_H
#define PVR_ROGUE_FWIF_RESETFRAMEWORK_H
#include <linux/bits.h>
#include <linux/types.h>
#include "pvr_rogue_fwif_shared.h"
struct rogue_fwif_rf_registers {
union {
u64 cdmreg_cdm_cb_base;
u64 cdmreg_cdm_ctrl_stream_base;
};
u64 cdmreg_cdm_cb_queue;
u64 cdmreg_cdm_cb;
};
struct rogue_fwif_rf_cmd {
/* THIS MUST BE THE LAST MEMBER OF THE CONTAINING STRUCTURE */
struct rogue_fwif_rf_registers fw_registers __aligned(8);
};
#define ROGUE_FWIF_RF_CMD_SIZE sizeof(struct rogue_fwif_rf_cmd)
#endif /* PVR_ROGUE_FWIF_RESETFRAMEWORK_H */

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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/* Copyright (c) 2023 Imagination Technologies Ltd. */
#ifndef PVR_ROGUE_FWIF_SHARED_H
#define PVR_ROGUE_FWIF_SHARED_H
#include <linux/compiler.h>
#include <linux/types.h>
#define ROGUE_FWIF_NUM_RTDATAS 2U
#define ROGUE_FWIF_NUM_GEOMDATAS 1U
#define ROGUE_FWIF_NUM_RTDATA_FREELISTS 2U
#define ROGUE_NUM_GEOM_CORES 1U
#define ROGUE_NUM_GEOM_CORES_SIZE 2U
/*
* Maximum number of UFOs in a CCB command.
* The number is based on having 32 sync prims (as originally), plus 32 sync
* checkpoints.
* Once the use of sync prims is no longer supported, we will retain
* the same total (64) as the number of sync checkpoints which may be
* supporting a fence is not visible to the client driver and has to
* allow for the number of different timelines involved in fence merges.
*/
#define ROGUE_FWIF_CCB_CMD_MAX_UFOS (32U + 32U)
/*
* This is a generic limit imposed on any DM (GEOMETRY,FRAGMENT,CDM,TDM,2D,TRANSFER)
* command passed through the bridge.
* Just across the bridge in the server, any incoming kick command size is
* checked against this maximum limit.
* In case the incoming command size is larger than the specified limit,
* the bridge call is retired with error.
*/
#define ROGUE_FWIF_DM_INDEPENDENT_KICK_CMD_SIZE (1024U)
#define ROGUE_FWIF_PRBUFFER_START (0)
#define ROGUE_FWIF_PRBUFFER_ZSBUFFER (0)
#define ROGUE_FWIF_PRBUFFER_MSAABUFFER (1)
#define ROGUE_FWIF_PRBUFFER_MAXSUPPORTED (2)
struct rogue_fwif_dma_addr {
aligned_u64 dev_addr;
u32 fw_addr;
u32 padding;
} __aligned(8);
struct rogue_fwif_ufo {
u32 addr;
u32 value;
};
#define ROGUE_FWIF_UFO_ADDR_IS_SYNC_CHECKPOINT (1)
struct rogue_fwif_sync_checkpoint {
u32 state;
u32 fw_ref_count;
};
struct rogue_fwif_cleanup_ctl {
/* Number of commands received by the FW */
u32 submitted_commands;
/* Number of commands executed by the FW */
u32 executed_commands;
} __aligned(8);
/*
* Used to share frame numbers across UM-KM-FW,
* frame number is set in UM,
* frame number is required in both KM for HTB and FW for FW trace.
*
* May be used to house Kick flags in the future.
*/
struct rogue_fwif_cmd_common {
/* associated frame number */
u32 frame_num;
};
/*
* Geometry and fragment commands require set of firmware addresses that are stored in the Kernel.
* Client has handle(s) to Kernel containers storing these addresses, instead of raw addresses. We
* have to patch/write these addresses in KM to prevent UM from controlling FW addresses directly.
* Typedefs for geometry and fragment commands are shared between Client and Firmware (both
* single-BVNC). Kernel is implemented in a multi-BVNC manner, so it can't use geometry|fragment
* CMD type definitions directly. Therefore we have a SHARED block that is shared between UM-KM-FW
* across all BVNC configurations.
*/
struct rogue_fwif_cmd_geom_frag_shared {
/* Common command attributes */
struct rogue_fwif_cmd_common cmn;
/*
* RTData associated with this command, this is used for context
* selection and for storing out HW-context, when TA is switched out for
* continuing later
*/
u32 hwrt_data_fw_addr;
/* Supported PR Buffers like Z/S/MSAA Scratch */
u32 pr_buffer_fw_addr[ROGUE_FWIF_PRBUFFER_MAXSUPPORTED];
};
/*
* Client Circular Command Buffer (CCCB) control structure.
* This is shared between the Server and the Firmware and holds byte offsets
* into the CCCB as well as the wrapping mask to aid wrap around. A given
* snapshot of this queue with Cmd 1 running on the GPU might be:
*
* Roff Doff Woff
* [..........|-1----------|=2===|=3===|=4===|~5~~~~|~6~~~~|~7~~~~|..........]
* < runnable commands >< !ready to run >
*
* Cmd 1 : Currently executing on the GPU data master.
* Cmd 2,3,4: Fence dependencies met, commands runnable.
* Cmd 5... : Fence dependency not met yet.
*/
struct rogue_fwif_cccb_ctl {
/* Host write offset into CCB. This must be aligned to 16 bytes. */
u32 write_offset;
/*
* Firmware read offset into CCB. Points to the command that is runnable
* on GPU, if R!=W
*/
u32 read_offset;
/*
* Firmware fence dependency offset. Points to commands not ready, i.e.
* fence dependencies are not met.
*/
u32 dep_offset;
/* Offset wrapping mask, total capacity in bytes of the CCB-1 */
u32 wrap_mask;
/* Only used if SUPPORT_AGP is present. */
u32 read_offset2;
/* Only used if SUPPORT_AGP4 is present. */
u32 read_offset3;
/* Only used if SUPPORT_AGP4 is present. */
u32 read_offset4;
u32 padding;
} __aligned(8);
#define ROGUE_FW_LOCAL_FREELIST (0)
#define ROGUE_FW_GLOBAL_FREELIST (1)
#define ROGUE_FW_FREELIST_TYPE_LAST ROGUE_FW_GLOBAL_FREELIST
#define ROGUE_FW_MAX_FREELISTS (ROGUE_FW_FREELIST_TYPE_LAST + 1U)
struct rogue_fwif_geom_registers_caswitch {
u64 geom_reg_vdm_context_state_base_addr;
u64 geom_reg_vdm_context_state_resume_addr;
u64 geom_reg_ta_context_state_base_addr;
struct {
u64 geom_reg_vdm_context_store_task0;
u64 geom_reg_vdm_context_store_task1;
u64 geom_reg_vdm_context_store_task2;
/* VDM resume state update controls */
u64 geom_reg_vdm_context_resume_task0;
u64 geom_reg_vdm_context_resume_task1;
u64 geom_reg_vdm_context_resume_task2;
u64 geom_reg_vdm_context_store_task3;
u64 geom_reg_vdm_context_store_task4;
u64 geom_reg_vdm_context_resume_task3;
u64 geom_reg_vdm_context_resume_task4;
} geom_state[2];
};
#define ROGUE_FWIF_GEOM_REGISTERS_CSWITCH_SIZE \
sizeof(struct rogue_fwif_geom_registers_caswitch)
struct rogue_fwif_cdm_registers_cswitch {
u64 cdmreg_cdm_context_pds0;
u64 cdmreg_cdm_context_pds1;
u64 cdmreg_cdm_terminate_pds;
u64 cdmreg_cdm_terminate_pds1;
/* CDM resume controls */
u64 cdmreg_cdm_resume_pds0;
u64 cdmreg_cdm_context_pds0_b;
u64 cdmreg_cdm_resume_pds0_b;
};
struct rogue_fwif_static_rendercontext_state {
/* Geom registers for ctx switch */
struct rogue_fwif_geom_registers_caswitch ctxswitch_regs[ROGUE_NUM_GEOM_CORES_SIZE]
__aligned(8);
};
#define ROGUE_FWIF_STATIC_RENDERCONTEXT_SIZE \
sizeof(struct rogue_fwif_static_rendercontext_state)
struct rogue_fwif_static_computecontext_state {
/* CDM registers for ctx switch */
struct rogue_fwif_cdm_registers_cswitch ctxswitch_regs __aligned(8);
};
#define ROGUE_FWIF_STATIC_COMPUTECONTEXT_SIZE \
sizeof(struct rogue_fwif_static_computecontext_state)
enum rogue_fwif_prbuffer_state {
ROGUE_FWIF_PRBUFFER_UNBACKED = 0,
ROGUE_FWIF_PRBUFFER_BACKED,
ROGUE_FWIF_PRBUFFER_BACKING_PENDING,
ROGUE_FWIF_PRBUFFER_UNBACKING_PENDING,
};
struct rogue_fwif_prbuffer {
/* Buffer ID*/
u32 buffer_id;
/* Needs On-demand Z/S/MSAA Buffer allocation */
bool on_demand __aligned(4);
/* Z/S/MSAA -Buffer state */
enum rogue_fwif_prbuffer_state state;
/* Cleanup state */
struct rogue_fwif_cleanup_ctl cleanup_sate;
/* Compatibility and other flags */
u32 prbuffer_flags;
} __aligned(8);
/* Last reset reason for a context. */
enum rogue_context_reset_reason {
/* No reset reason recorded */
ROGUE_CONTEXT_RESET_REASON_NONE = 0,
/* Caused a reset due to locking up */
ROGUE_CONTEXT_RESET_REASON_GUILTY_LOCKUP = 1,
/* Affected by another context locking up */
ROGUE_CONTEXT_RESET_REASON_INNOCENT_LOCKUP = 2,
/* Overran the global deadline */
ROGUE_CONTEXT_RESET_REASON_GUILTY_OVERRUNING = 3,
/* Affected by another context overrunning */
ROGUE_CONTEXT_RESET_REASON_INNOCENT_OVERRUNING = 4,
/* Forced reset to ensure scheduling requirements */
ROGUE_CONTEXT_RESET_REASON_HARD_CONTEXT_SWITCH = 5,
/* FW Safety watchdog triggered */
ROGUE_CONTEXT_RESET_REASON_FW_WATCHDOG = 12,
/* FW page fault (no HWR) */
ROGUE_CONTEXT_RESET_REASON_FW_PAGEFAULT = 13,
/* FW execution error (GPU reset requested) */
ROGUE_CONTEXT_RESET_REASON_FW_EXEC_ERR = 14,
/* Host watchdog detected FW error */
ROGUE_CONTEXT_RESET_REASON_HOST_WDG_FW_ERR = 15,
/* Geometry DM OOM event is not allowed */
ROGUE_CONTEXT_GEOM_OOM_DISABLED = 16,
};
struct rogue_context_reset_reason_data {
enum rogue_context_reset_reason reset_reason;
u32 reset_ext_job_ref;
};
#include "pvr_rogue_fwif_shared_check.h"
#endif /* PVR_ROGUE_FWIF_SHARED_H */

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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/* Copyright (c) 2023 Imagination Technologies Ltd. */
#ifndef PVR_ROGUE_FWIF_SHARED_CHECK_H
#define PVR_ROGUE_FWIF_SHARED_CHECK_H
#include <linux/build_bug.h>
#define OFFSET_CHECK(type, member, offset) \
static_assert(offsetof(type, member) == (offset), \
"offsetof(" #type ", " #member ") incorrect")
#define SIZE_CHECK(type, size) \
static_assert(sizeof(type) == (size), #type " is incorrect size")
OFFSET_CHECK(struct rogue_fwif_dma_addr, dev_addr, 0);
OFFSET_CHECK(struct rogue_fwif_dma_addr, fw_addr, 8);
SIZE_CHECK(struct rogue_fwif_dma_addr, 16);
OFFSET_CHECK(struct rogue_fwif_ufo, addr, 0);
OFFSET_CHECK(struct rogue_fwif_ufo, value, 4);
SIZE_CHECK(struct rogue_fwif_ufo, 8);
OFFSET_CHECK(struct rogue_fwif_cleanup_ctl, submitted_commands, 0);
OFFSET_CHECK(struct rogue_fwif_cleanup_ctl, executed_commands, 4);
SIZE_CHECK(struct rogue_fwif_cleanup_ctl, 8);
OFFSET_CHECK(struct rogue_fwif_cccb_ctl, write_offset, 0);
OFFSET_CHECK(struct rogue_fwif_cccb_ctl, read_offset, 4);
OFFSET_CHECK(struct rogue_fwif_cccb_ctl, dep_offset, 8);
OFFSET_CHECK(struct rogue_fwif_cccb_ctl, wrap_mask, 12);
OFFSET_CHECK(struct rogue_fwif_cccb_ctl, read_offset2, 16);
OFFSET_CHECK(struct rogue_fwif_cccb_ctl, read_offset3, 20);
OFFSET_CHECK(struct rogue_fwif_cccb_ctl, read_offset4, 24);
SIZE_CHECK(struct rogue_fwif_cccb_ctl, 32);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_reg_vdm_context_state_base_addr, 0);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_reg_vdm_context_state_resume_addr, 8);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_reg_ta_context_state_base_addr, 16);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_state[0].geom_reg_vdm_context_store_task0, 24);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_state[0].geom_reg_vdm_context_store_task1, 32);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_state[0].geom_reg_vdm_context_store_task2, 40);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_state[0].geom_reg_vdm_context_resume_task0, 48);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_state[0].geom_reg_vdm_context_resume_task1, 56);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_state[0].geom_reg_vdm_context_resume_task2, 64);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_state[0].geom_reg_vdm_context_store_task3, 72);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_state[0].geom_reg_vdm_context_store_task4, 80);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_state[0].geom_reg_vdm_context_resume_task3, 88);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_state[0].geom_reg_vdm_context_resume_task4, 96);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_state[1].geom_reg_vdm_context_store_task0, 104);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_state[1].geom_reg_vdm_context_store_task1, 112);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_state[1].geom_reg_vdm_context_store_task2, 120);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_state[1].geom_reg_vdm_context_resume_task0, 128);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_state[1].geom_reg_vdm_context_resume_task1, 136);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_state[1].geom_reg_vdm_context_resume_task2, 144);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_state[1].geom_reg_vdm_context_store_task3, 152);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_state[1].geom_reg_vdm_context_store_task4, 160);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_state[1].geom_reg_vdm_context_resume_task3, 168);
OFFSET_CHECK(struct rogue_fwif_geom_registers_caswitch,
geom_state[1].geom_reg_vdm_context_resume_task4, 176);
SIZE_CHECK(struct rogue_fwif_geom_registers_caswitch, 184);
OFFSET_CHECK(struct rogue_fwif_cdm_registers_cswitch, cdmreg_cdm_context_pds0, 0);
OFFSET_CHECK(struct rogue_fwif_cdm_registers_cswitch, cdmreg_cdm_context_pds1, 8);
OFFSET_CHECK(struct rogue_fwif_cdm_registers_cswitch, cdmreg_cdm_terminate_pds, 16);
OFFSET_CHECK(struct rogue_fwif_cdm_registers_cswitch, cdmreg_cdm_terminate_pds1, 24);
OFFSET_CHECK(struct rogue_fwif_cdm_registers_cswitch, cdmreg_cdm_resume_pds0, 32);
OFFSET_CHECK(struct rogue_fwif_cdm_registers_cswitch, cdmreg_cdm_context_pds0_b, 40);
OFFSET_CHECK(struct rogue_fwif_cdm_registers_cswitch, cdmreg_cdm_resume_pds0_b, 48);
SIZE_CHECK(struct rogue_fwif_cdm_registers_cswitch, 56);
OFFSET_CHECK(struct rogue_fwif_static_rendercontext_state, ctxswitch_regs, 0);
SIZE_CHECK(struct rogue_fwif_static_rendercontext_state, 368);
OFFSET_CHECK(struct rogue_fwif_static_computecontext_state, ctxswitch_regs, 0);
SIZE_CHECK(struct rogue_fwif_static_computecontext_state, 56);
OFFSET_CHECK(struct rogue_fwif_cmd_common, frame_num, 0);
SIZE_CHECK(struct rogue_fwif_cmd_common, 4);
OFFSET_CHECK(struct rogue_fwif_cmd_geom_frag_shared, cmn, 0);
OFFSET_CHECK(struct rogue_fwif_cmd_geom_frag_shared, hwrt_data_fw_addr, 4);
OFFSET_CHECK(struct rogue_fwif_cmd_geom_frag_shared, pr_buffer_fw_addr, 8);
SIZE_CHECK(struct rogue_fwif_cmd_geom_frag_shared, 16);
#endif /* PVR_ROGUE_FWIF_SHARED_CHECK_H */

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drivers/gpu/drm/imagination/pvr_rogue_fwif_stream.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/* Copyright (c) 2023 Imagination Technologies Ltd. */
#ifndef PVR_ROGUE_FWIF_STREAM_H
#define PVR_ROGUE_FWIF_STREAM_H
/**
* DOC: Streams
*
* Commands are submitted to the kernel driver in the form of streams.
*
* A command stream has the following layout :
* - A 64-bit header containing:
* * A u32 containing the length of the main stream inclusive of the length of the header.
* * A u32 for padding.
* - The main stream data.
* - The extension stream (optional), which is composed of:
* * One or more headers.
* * The extension stream data, corresponding to the extension headers.
*
* The main stream provides the base command data. This has a fixed layout based on the features
* supported by a given GPU.
*
* The extension stream provides the command parameters that are required for BRNs & ERNs for the
* current GPU. This stream is comprised of one or more headers, followed by data for each given
* BRN/ERN.
*
* Each header is a u32 containing a bitmask of quirks & enhancements in the extension stream, a
* "type" field determining the set of quirks & enhancements the bitmask represents, and a
* continuation bit determining whether any more headers are present. The headers are then followed
* by command data; this is specific to each quirk/enhancement. All unused / reserved bits in the
* header must be set to 0.
*
* All parameters and headers in the main and extension streams must be naturally aligned.
*
* If a parameter appears in both the main and extension streams, then the extension parameter is
* used.
*/
/*
* Stream extension header definition
*/
#define PVR_STREAM_EXTHDR_TYPE_SHIFT 29U
#define PVR_STREAM_EXTHDR_TYPE_MASK (7U << PVR_STREAM_EXTHDR_TYPE_SHIFT)
#define PVR_STREAM_EXTHDR_TYPE_MAX 8U
#define PVR_STREAM_EXTHDR_CONTINUATION BIT(28U)
#define PVR_STREAM_EXTHDR_DATA_MASK ~(PVR_STREAM_EXTHDR_TYPE_MASK | PVR_STREAM_EXTHDR_CONTINUATION)
/*
* Stream extension header - Geometry 0
*/
#define PVR_STREAM_EXTHDR_TYPE_GEOM0 0U
#define PVR_STREAM_EXTHDR_GEOM0_BRN49927 BIT(0U)
#define PVR_STREAM_EXTHDR_GEOM0_VALID PVR_STREAM_EXTHDR_GEOM0_BRN49927
/*
* Stream extension header - Fragment 0
*/
#define PVR_STREAM_EXTHDR_TYPE_FRAG0 0U
#define PVR_STREAM_EXTHDR_FRAG0_BRN47217 BIT(0U)
#define PVR_STREAM_EXTHDR_FRAG0_BRN49927 BIT(1U)
#define PVR_STREAM_EXTHDR_FRAG0_VALID PVR_STREAM_EXTHDR_FRAG0_BRN49927
/*
* Stream extension header - Compute 0
*/
#define PVR_STREAM_EXTHDR_TYPE_COMPUTE0 0U
#define PVR_STREAM_EXTHDR_COMPUTE0_BRN49927 BIT(0U)
#define PVR_STREAM_EXTHDR_COMPUTE0_VALID PVR_STREAM_EXTHDR_COMPUTE0_BRN49927
#endif /* PVR_ROGUE_FWIF_STREAM_H */