dt-bindings: mfd: aspeed-lpc: Convert to YAML schema
Convert the bindings of Aspeed LPC from text file into YAML schema. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Link: https://lore.kernel.org/r/20210927023053.6728-3-chiawei_wang@aspeedtech.com [robh: Add 'additionalProperties: false' in child nodes and #reset-cells] Signed-off-by: Rob Herring <robh@kernel.org>
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Chia-Wei Wang
Rob Herring
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a2db23c110
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======================================================================
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Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
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======================================================================
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The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
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peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
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primary use case of the Aspeed LPC controller is as a slave on the bus
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(typically in a Baseboard Management Controller SoC), but under certain
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conditions it can also take the role of bus master.
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The LPC controller is represented as a multi-function device to account for the
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mix of functionality, which includes, but is not limited to:
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* An IPMI Block Transfer[2] Controller
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* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
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physical properties of some LPC pins, configuration of serial IRQs, and
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APB-to-LPC bridging amonst other functions.
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* An LPC Host Interface Controller: Manages functions exposed to the host such
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as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
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management and bus snoop configuration.
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* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom
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hardware management protocols for handover between the host and baseboard
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management controller.
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Additionally the state of the LPC controller influences the pinmux
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configuration, therefore the host portion of the controller is exposed as a
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syscon as a means to arbitrate access.
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[0] http://www.intel.com/design/chipsets/industry/25128901.pdf
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[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4
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[2] https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
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[3] https://en.wikipedia.org/wiki/Super_I/O
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Required properties
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===================
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- compatible: One of:
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"aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"
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"aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"
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"aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"
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- reg: contains the physical address and length values of the Aspeed
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LPC memory region.
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- #address-cells: <1>
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- #size-cells: <1>
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- ranges: Maps 0 to the physical address and length of the LPC memory
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region
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Example:
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lpc: lpc@1e789000 {
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compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
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reg = <0x1e789000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x1e789000 0x1000>;
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lpc_snoop: lpc-snoop@0 {
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compatible = "aspeed,ast2600-lpc-snoop";
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reg = <0x0 0x80>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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snoop-ports = <0x80>;
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};
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};
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LPC Host Interface Controller
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-------------------
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The LPC Host Interface Controller manages functions exposed to the host such as
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LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
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management and bus snoop configuration.
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Required properties:
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- compatible: One of:
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"aspeed,ast2400-lpc-ctrl";
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"aspeed,ast2500-lpc-ctrl";
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"aspeed,ast2600-lpc-ctrl";
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- reg: contains offset/length values of the host interface controller
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memory regions
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- clocks: contains a phandle to the syscon node describing the clocks.
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There should then be one cell representing the clock to use
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Optional properties:
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- memory-region: A phandle to a reserved_memory region to be used for the LPC
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to AHB mapping
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- flash: A phandle to the SPI flash controller containing the flash to
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be exposed over the LPC to AHB mapping
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Example:
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lpc_ctrl: lpc-ctrl@80 {
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compatible = "aspeed,ast2500-lpc-ctrl";
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reg = <0x80 0x80>;
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clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
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memory-region = <&flash_memory>;
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flash = <&spi>;
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};
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LPC Host Controller
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-------------------
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The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
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between the host and the baseboard management controller. The registers exist
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in the "host" portion of the Aspeed LPC controller, which must be the parent of
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the LPC host controller node.
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Required properties:
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- compatible: One of:
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"aspeed,ast2400-lhc";
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"aspeed,ast2500-lhc";
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"aspeed,ast2600-lhc";
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- reg: contains offset/length values of the LHC memory regions. In the
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AST2400 and AST2500 there are two regions.
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Example:
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lhc: lhc@a0 {
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compatible = "aspeed,ast2500-lhc";
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reg = <0xa0 0x24 0xc8 0x8>;
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};
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LPC reset control
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-----------------
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The UARTs present in the ASPEED SoC can have their resets tied to the reset
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state of the LPC bus. Some systems may chose to modify this configuration.
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Required properties:
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- compatible: One of:
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"aspeed,ast2600-lpc-reset";
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"aspeed,ast2500-lpc-reset";
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"aspeed,ast2400-lpc-reset";
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- reg: offset and length of the IP in the LHC memory region
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- #reset-controller indicates the number of reset cells expected
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Example:
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lpc_reset: reset-controller@98 {
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compatible = "aspeed,ast2500-lpc-reset";
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reg = <0x98 0x4>;
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#reset-cells = <1>;
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};
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195
Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
Normal file
195
Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
Normal file
@ -0,0 +1,195 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# # Copyright (c) 2021 Aspeed Tehchnology Inc.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Aspeed Low Pin Count (LPC) Bus Controller
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maintainers:
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- Andrew Jeffery <andrew@aj.id.au>
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- Chia-Wei Wang <chiawei_wang@aspeedtech.com>
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description:
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The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
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peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
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primary use case of the Aspeed LPC controller is as a slave on the bus
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(typically in a Baseboard Management Controller SoC), but under certain
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conditions it can also take the role of bus master.
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The LPC controller is represented as a multi-function device to account for the
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mix of functionality, which includes, but is not limited to
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* An IPMI Block Transfer[2] Controller
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* An LPC Host Interface Controller manages functions exposed to the host such
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as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
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management and bus snoop configuration.
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* A set of SuperIO[3] scratch registers enableing implementation of e.g. custom
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hardware management protocols for handover between the host and baseboard
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management controller.
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Additionally the state of the LPC controller influences the pinmux
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configuration, therefore the host portion of the controller is exposed as a
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syscon as a means to arbitrate access.
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properties:
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compatible:
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items:
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- enum:
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- aspeed,ast2400-lpc-v2
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- aspeed,ast2500-lpc-v2
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- aspeed,ast2600-lpc-v2
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- const: simple-mfd
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- const: syscon
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reg:
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maxItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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ranges: true
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patternProperties:
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"^lpc-ctrl@[0-9a-f]+$":
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type: object
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additionalProperties: false
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description: |
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The LPC Host Interface Controller manages functions exposed to the host such as
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LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management
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and bus snoop configuration.
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properties:
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compatible:
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items:
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- enum:
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- aspeed,ast2400-lpc-ctrl
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- aspeed,ast2500-lpc-ctrl
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- aspeed,ast2600-lpc-ctrl
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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memory-region:
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maxItems: 1
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description: handle to memory reservation for the LPC to AHB mapping region
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flash:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: The SPI flash controller containing the flash to be exposed over the LPC to AHB mapping
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required:
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- compatible
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- clocks
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"^reset-controller@[0-9a-f]+$":
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type: object
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additionalProperties: false
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description:
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The UARTs present in the ASPEED SoC can have their resets tied to the reset
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state of the LPC bus. Some systems may chose to modify this configuration
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properties:
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compatible:
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items:
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- enum:
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- aspeed,ast2400-lpc-reset
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- aspeed,ast2500-lpc-reset
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- aspeed,ast2600-lpc-reset
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reg:
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maxItems: 1
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'#reset-cells':
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const: 1
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required:
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- compatible
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- '#reset-cells'
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"^lpc-snoop@[0-9a-f]+$":
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type: object
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additionalProperties: false
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description:
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The LPC snoop interface allows the BMC to listen on and record the data
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bytes written by the Host to the targeted LPC I/O pots.
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properties:
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compatible:
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items:
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- enum:
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- aspeed,ast2400-lpc-snoop
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- aspeed,ast2500-lpc-snoop
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- aspeed,ast2600-lpc-snoop
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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snoop-ports:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description: The LPC I/O ports to snoop
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required:
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- compatible
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- interrupts
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- snoop-ports
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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- ranges
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additionalProperties:
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type: object
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/ast2600-clock.h>
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lpc: lpc@1e789000 {
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compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
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reg = <0x1e789000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x1e789000 0x1000>;
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lpc_ctrl: lpc-ctrl@80 {
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compatible = "aspeed,ast2600-lpc-ctrl";
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reg = <0x80 0x80>;
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clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
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memory-region = <&flash_memory>;
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flash = <&spi>;
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};
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lpc_reset: reset-controller@98 {
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compatible = "aspeed,ast2600-lpc-reset";
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reg = <0x98 0x4>;
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#reset-cells = <1>;
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};
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lpc_snoop: lpc-snoop@90 {
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compatible = "aspeed,ast2600-lpc-snoop";
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reg = <0x90 0x8>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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snoop-ports = <0x80>;
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};
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};
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