x86/entry: Add kernel IBRS implementation
commit 2dbb887e875b1de3ca8f40ddf26bcfe55798c609 upstream. Implement Kernel IBRS - currently the only known option to mitigate RSB underflow speculation issues on Skylake hardware. Note: since IBRS_ENTER requires fuller context established than UNTRAIN_RET, it must be placed after it. However, since UNTRAIN_RET itself implies a RET, it must come after IBRS_ENTER. This means IBRS_ENTER needs to also move UNTRAIN_RET. Note 2: KERNEL_IBRS is sub-optimal for XenPV. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Josh Poimboeuf <jpoimboe@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> [cascardo: conflict at arch/x86/entry/entry_64.S, skip_r11rcx] [cascardo: conflict at arch/x86/entry/entry_64_compat.S] [cascardo: conflict fixups, no ANNOTATE_NOENDBR] [cascardo: entry fixups because of missing UNTRAIN_RET] [cascardo: conflicts on fsgsbase] Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Peter Zijlstra
Greg Kroah-Hartman
parent
fd32a31553
commit
a3111faed5
@ -6,6 +6,8 @@
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#include <asm/percpu.h>
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#include <asm/asm-offsets.h>
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#include <asm/processor-flags.h>
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#include <asm/msr.h>
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#include <asm/nospec-branch.h>
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/*
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@ -308,6 +310,62 @@ For 32-bit we have the following conventions - kernel is built with
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#endif
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/*
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* IBRS kernel mitigation for Spectre_v2.
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*
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* Assumes full context is established (PUSH_REGS, CR3 and GS) and it clobbers
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* the regs it uses (AX, CX, DX). Must be called before the first RET
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* instruction (NOTE! UNTRAIN_RET includes a RET instruction)
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*
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* The optional argument is used to save/restore the current value,
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* which is used on the paranoid paths.
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*
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* Assumes x86_spec_ctrl_{base,current} to have SPEC_CTRL_IBRS set.
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*/
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.macro IBRS_ENTER save_reg
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ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_KERNEL_IBRS
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movl $MSR_IA32_SPEC_CTRL, %ecx
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.ifnb \save_reg
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rdmsr
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shl $32, %rdx
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or %rdx, %rax
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mov %rax, \save_reg
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test $SPEC_CTRL_IBRS, %eax
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jz .Ldo_wrmsr_\@
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lfence
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jmp .Lend_\@
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.Ldo_wrmsr_\@:
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.endif
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movq PER_CPU_VAR(x86_spec_ctrl_current), %rdx
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movl %edx, %eax
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shr $32, %rdx
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wrmsr
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.Lend_\@:
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.endm
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/*
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* Similar to IBRS_ENTER, requires KERNEL GS,CR3 and clobbers (AX, CX, DX)
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* regs. Must be called after the last RET.
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*/
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.macro IBRS_EXIT save_reg
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ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_KERNEL_IBRS
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movl $MSR_IA32_SPEC_CTRL, %ecx
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.ifnb \save_reg
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mov \save_reg, %rdx
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.else
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movq PER_CPU_VAR(x86_spec_ctrl_current), %rdx
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andl $(~SPEC_CTRL_IBRS), %edx
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.endif
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movl %edx, %eax
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shr $32, %rdx
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wrmsr
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.Lend_\@:
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.endm
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/*
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* Mitigate Spectre v1 for conditional swapgs code paths.
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*
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@ -172,6 +172,10 @@ GLOBAL(entry_SYSCALL_64_after_hwframe)
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/* IRQs are off. */
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movq %rax, %rdi
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movq %rsp, %rsi
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/* clobbers %rax, make sure it is after saving the syscall nr */
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IBRS_ENTER
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call do_syscall_64 /* returns with IRQs disabled */
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TRACE_IRQS_IRETQ /* we're about to change IF */
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@ -248,6 +252,7 @@ GLOBAL(entry_SYSCALL_64_after_hwframe)
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* perf profiles. Nothing jumps here.
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*/
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syscall_return_via_sysret:
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IBRS_EXIT
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POP_REGS pop_rdi=0
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/*
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@ -621,6 +626,7 @@ GLOBAL(retint_user)
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TRACE_IRQS_IRETQ
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GLOBAL(swapgs_restore_regs_and_return_to_usermode)
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IBRS_EXIT
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#ifdef CONFIG_DEBUG_ENTRY
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/* Assert that pt_regs indicates user mode. */
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testb $3, CS(%rsp)
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@ -1247,7 +1253,13 @@ ENTRY(paranoid_entry)
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*/
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FENCE_SWAPGS_KERNEL_ENTRY
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ret
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/*
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* Once we have CR3 and %GS setup save and set SPEC_CTRL. Just like
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* CR3 above, keep the old value in a callee saved register.
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*/
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IBRS_ENTER save_reg=%r15
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RET
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END(paranoid_entry)
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/*
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@ -1275,12 +1287,20 @@ ENTRY(paranoid_exit)
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jmp .Lparanoid_exit_restore
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.Lparanoid_exit_no_swapgs:
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TRACE_IRQS_IRETQ_DEBUG
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/*
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* Must restore IBRS state before both CR3 and %GS since we need access
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* to the per-CPU x86_spec_ctrl_shadow variable.
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*/
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IBRS_EXIT save_reg=%r15
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/* Always restore stashed CR3 value (see paranoid_entry) */
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RESTORE_CR3 scratch_reg=%rbx save_reg=%r14
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.Lparanoid_exit_restore:
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jmp restore_regs_and_return_to_kernel
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END(paranoid_exit)
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/*
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* Save all registers in pt_regs, and switch GS if needed.
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*/
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@ -1300,6 +1320,7 @@ ENTRY(error_entry)
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FENCE_SWAPGS_USER_ENTRY
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/* We have user CR3. Change to kernel CR3. */
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SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
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IBRS_ENTER
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.Lerror_entry_from_usermode_after_swapgs:
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/* Put us onto the real thread stack. */
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@ -1355,6 +1376,7 @@ ENTRY(error_entry)
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SWAPGS
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FENCE_SWAPGS_USER_ENTRY
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SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
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IBRS_ENTER
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/*
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* Pretend that the exception came from user mode: set up pt_regs
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@ -1460,6 +1482,8 @@ ENTRY(nmi)
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PUSH_AND_CLEAR_REGS rdx=(%rdx)
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ENCODE_FRAME_POINTER
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IBRS_ENTER
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/*
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* At this point we no longer need to worry about stack damage
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* due to nesting -- we're on the normal thread stack and we're
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@ -1683,6 +1707,9 @@ end_repeat_nmi:
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movq $-1, %rsi
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call do_nmi
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/* Always restore stashed SPEC_CTRL value (see paranoid_entry) */
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IBRS_EXIT save_reg=%r15
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/* Always restore stashed CR3 value (see paranoid_entry) */
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RESTORE_CR3 scratch_reg=%r15 save_reg=%r14
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@ -4,7 +4,6 @@
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*
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* Copyright 2000-2002 Andi Kleen, SuSE Labs.
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*/
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#include "calling.h"
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#include <asm/asm-offsets.h>
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#include <asm/current.h>
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#include <asm/errno.h>
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@ -17,6 +16,8 @@
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#include <linux/linkage.h>
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#include <linux/err.h>
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#include "calling.h"
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.section .entry.text, "ax"
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/*
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@ -106,6 +107,8 @@ ENTRY(entry_SYSENTER_compat)
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xorl %r15d, %r15d /* nospec r15 */
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cld
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IBRS_ENTER
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/*
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* SYSENTER doesn't filter flags, so we need to clear NT and AC
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* ourselves. To save a few cycles, we can check whether
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@ -253,6 +256,8 @@ GLOBAL(entry_SYSCALL_compat_after_hwframe)
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*/
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TRACE_IRQS_OFF
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IBRS_ENTER
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movq %rsp, %rdi
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call do_fast_syscall_32
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/* XEN PV guests always use IRET path */
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@ -267,6 +272,9 @@ sysret32_from_system_call:
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*/
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STACKLEAK_ERASE
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TRACE_IRQS_ON /* User mode traces as IRQs on. */
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IBRS_EXIT
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movq RBX(%rsp), %rbx /* pt_regs->rbx */
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movq RBP(%rsp), %rbp /* pt_regs->rbp */
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movq EFLAGS(%rsp), %r11 /* pt_regs->flags (in r11) */
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@ -408,6 +416,7 @@ ENTRY(entry_INT80_compat)
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* gate turned them off.
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*/
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TRACE_IRQS_OFF
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IBRS_ENTER
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movq %rsp, %rdi
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call do_int80_syscall_32
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@ -203,7 +203,7 @@
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#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
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#define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */
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#define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */
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/* FREE! ( 7*32+12) */
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#define X86_FEATURE_KERNEL_IBRS ( 7*32+12) /* "" Set/clear IBRS on kernel entry/exit */
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/* FREE! ( 7*32+13) */
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#define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */
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#define X86_FEATURE_CDP_L2 ( 7*32+15) /* Code and Data Prioritization L2 */
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