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- Remove dev_err() when used with platform_get_irq (Stephen Boyd)

Browse Source 
- Add DT binding and new compatible for Allwinner sun4i (Maxime Ripard)
 
 - Register the Atmel tcb clocksource for delays (Alexandre Belloni)
 
 - Add a clock divider for the Freescale imx platforms and new timer node
   in the DT (Anson Huang)
 
 - Use DIV_ROUND_CLOSEST macro for the Renesas OSTM (Geert Uytterhoeven)
 
 - Fix GENMASK and timer operation for the npcm timer (Avi Fishman)
 
 - Fix timer-of showing an error message when EPROBE_DEFER is
   returned (Jon Hunter)
 
 - Add new SoC DT binding and match for Renesas timers (Magnus Damm)
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCAAdFiEEGn3N4YVz0WNVyHskqDIjiipP6E8FAl1kXkMACgkQqDIjiipP
 6E+ueQf7BpqpjmRa/YVUXXoX9G85nuSdwWvW8v1J14Drly7GvD0aYOX/TSzdqvV3
 1cEVDiSSWD/tdp5e8L+ah1c60EvEv1O7eAhvRj3miaI/M35RyluL9yCntjtxSFT9
 D9PHeR9u0fDzOfabJ04KrWOwwEyS5/BJfhsBX6rfF0AQkHfxNoU4VdwEBXDZkyfZ
 oVRcu75AIvvlqec32kCCF5veU3I4tdYYcnEKD3IEOKMbu84JUrVZtX3SdpJ9Pd1M
 pqm2ldP3S1Q1zryXOGJ9yzhrnhqO+jIoMQP0KscGQ7iQJhVvtOwDhMVp89ThNpZm
 PLw7chPsBLZrP2D6J7OvJFpRBDqCrw==
 =wXfz
 -----END PGP SIGNATURE-----

Merge tag 'timers-v5.4' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core

Pull clocksource/events updates from Daniel Lezcano:

 - Remove dev_err() when used with platform_get_irq (Stephen Boyd)

 - Add DT binding and new compatible for Allwinner sun4i (Maxime Ripard)

 - Register the Atmel tcb clocksource for delays (Alexandre Belloni)

 - Add a clock divider for the Freescale imx platforms and new timer node
   in the DT (Anson Huang)

 - Use DIV_ROUND_CLOSEST macro for the Renesas OSTM (Geert Uytterhoeven)

 - Fix GENMASK and timer operation for the npcm timer (Avi Fishman)

 - Fix timer-of showing an error message when EPROBE_DEFER is
   returned (Jon Hunter)

 - Add new SoC DT binding and match for Renesas timers (Magnus Damm)
This commit is contained in:
Thomas Gleixner 2019-08-27 00:42:06 +02:00
commit a42e43c3de
18 changed files with 275 additions and 85 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

102
Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml Normal file
View File

@ -0,0 +1,102 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/allwinner,sun4i-a10-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 Timer Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <maxime.ripard@bootlin.com>
properties:
compatible:
enum:
- allwinner,sun4i-a10-timer
- allwinner,sun8i-a23-timer
- allwinner,sun8i-v3s-timer
- allwinner,suniv-f1c100s-timer
reg:
maxItems: 1
interrupts:
description:
List of timers interrupts
clocks:
maxItems: 1
allOf:
- if:
properties:
compatible:
items:
const: allwinner,sun4i-a10-timer
then:
properties:
interrupts:
minItems: 6
maxItems: 6
- if:
properties:
compatible:
items:
const: allwinner,sun8i-a23-timer
then:
properties:
interrupts:
minItems: 2
maxItems: 2
- if:
properties:
compatible:
items:
const: allwinner,sun8i-v3s-timer
then:
properties:
interrupts:
minItems: 3
maxItems: 3
- if:
properties:
compatible:
items:
const: allwinner,suniv-f1c100s-timer
then:
properties:
interrupts:
minItems: 3
maxItems: 3
required:
- compatible
- reg
- interrupts
- clocks
additionalProperties: false
examples:
- |
timer {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0x400>;
interrupts = <22>,
<23>,
<24>,
<25>,
<67>,
<68>;
clocks = <&osc>;
};
...

19
Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
View File

@ -1,19 +0,0 @@
Allwinner A1X SoCs Timer Controller
Required properties:
- compatible : should be one of the following:
"allwinner,sun4i-a10-timer"
"allwinner,suniv-f1c100s-timer"
- reg : Specifies base physical address and size of the registers.
- interrupts : The interrupt of the first timer
- clocks: phandle to the source clock (usually a 24 MHz fixed clock)
Example:
timer {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0x400>;
interrupts = <22>;
clocks = <&osc>;
};

26
Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
View File

@ -1,26 +0,0 @@
Allwinner SoCs High Speed Timer Controller
Required properties:
- compatible : should be "allwinner,sun5i-a13-hstimer" or
"allwinner,sun7i-a20-hstimer"
- reg : Specifies base physical address and size of the registers.
- interrupts : The interrupts of these timers (2 for the sun5i IP, 4 for the sun7i
one)
- clocks: phandle to the source clock (usually the AHB clock)
Optional properties:
- resets: phandle to a reset controller asserting the timer
Example:
timer@1c60000 {
compatible = "allwinner,sun7i-a20-hstimer";
reg = <0x01c60000 0x1000>;
interrupts = <0 51 1>,
<0 52 1>,
<0 53 1>,
<0 54 1>;
clocks = <&ahb1_gates 19>;
resets = <&ahb1rst 19>;
};

79
Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml Normal file
View File

@ -0,0 +1,79 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/allwinner,sun5i-a13-hstimer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A13 High-Speed Timer Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <maxime.ripard@bootlin.com>
properties:
compatible:
oneOf:
- const: allwinner,sun5i-a13-hstimer
- const: allwinner,sun7i-a20-hstimer
- items:
- const: allwinner,sun6i-a31-hstimer
- const: allwinner,sun7i-a20-hstimer
reg:
maxItems: 1
interrupts:
minItems: 2
maxItems: 4
items:
- description: Timer 0 Interrupt
- description: Timer 1 Interrupt
- description: Timer 2 Interrupt
- description: Timer 3 Interrupt
clocks:
maxItems: 1
resets:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
if:
properties:
compatible:
items:
const: allwinner,sun5i-a13-hstimer
then:
properties:
interrupts:
minItems: 2
maxItems: 2
else:
properties:
interrupts:
minItems: 4
maxItems: 4
additionalProperties: false
examples:
- |
timer@1c60000 {
compatible = "allwinner,sun7i-a20-hstimer";
reg = <0x01c60000 0x1000>;
interrupts = <0 51 1>,
<0 52 1>,
<0 53 1>,
<0 54 1>;
clocks = <&ahb1_gates 19>;
resets = <&ahb1rst 19>;
};
...

40
Documentation/devicetree/bindings/timer/renesas,cmt.txt
View File

@ -12,16 +12,13 @@ datasheets.
Required Properties:
- compatible: must contain one or more of the following:
- "renesas,cmt-48-sh73a0" for the sh73A0 48-bit CMT
(CMT1)
- "renesas,cmt-48-r8a7740" for the r8a7740 48-bit CMT
(CMT1)
- "renesas,cmt-48" for all non-second generation 48-bit CMT
(CMT1 on sh73a0 and r8a7740)
This is a fallback for the above renesas,cmt-48-* entries.
- "renesas,r8a73a4-cmt0" for the 32-bit CMT0 device included in r8a73a4.
- "renesas,r8a73a4-cmt1" for the 48-bit CMT1 device included in r8a73a4.
- "renesas,r8a7740-cmt0" for the 32-bit CMT0 device included in r8a7740.
- "renesas,r8a7740-cmt1" for the 48-bit CMT1 device included in r8a7740.
- "renesas,r8a7740-cmt2" for the 32-bit CMT2 device included in r8a7740.
- "renesas,r8a7740-cmt3" for the 32-bit CMT3 device included in r8a7740.
- "renesas,r8a7740-cmt4" for the 32-bit CMT4 device included in r8a7740.
- "renesas,r8a7743-cmt0" for the 32-bit CMT0 device included in r8a7743.
- "renesas,r8a7743-cmt1" for the 48-bit CMT1 device included in r8a7743.
- "renesas,r8a7744-cmt0" for the 32-bit CMT0 device included in r8a7744.
@ -31,29 +28,38 @@ Required Properties:
- "renesas,r8a77470-cmt0" for the 32-bit CMT0 device included in r8a77470.
- "renesas,r8a77470-cmt1" for the 48-bit CMT1 device included in r8a77470.
- "renesas,r8a774a1-cmt0" for the 32-bit CMT0 device included in r8a774a1.
- "renesas,r8a774a1-cmt1" for the 48-bit CMT1 device included in r8a774a1.
- "renesas,r8a774a1-cmt1" for the 48-bit CMT devices included in r8a774a1.
- "renesas,r8a774c0-cmt0" for the 32-bit CMT0 device included in r8a774c0.
- "renesas,r8a774c0-cmt1" for the 48-bit CMT1 device included in r8a774c0.
- "renesas,r8a774c0-cmt1" for the 48-bit CMT devices included in r8a774c0.
- "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790.
- "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790.
- "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791.
- "renesas,r8a7791-cmt1" for the 48-bit CMT1 device included in r8a7791.
- "renesas,r8a7792-cmt0" for the 32-bit CMT0 device included in r8a7792.
- "renesas,r8a7792-cmt1" for the 48-bit CMT1 device included in r8a7792.
- "renesas,r8a7793-cmt0" for the 32-bit CMT0 device included in r8a7793.
- "renesas,r8a7793-cmt1" for the 48-bit CMT1 device included in r8a7793.
- "renesas,r8a7794-cmt0" for the 32-bit CMT0 device included in r8a7794.
- "renesas,r8a7794-cmt1" for the 48-bit CMT1 device included in r8a7794.
- "renesas,r8a7795-cmt0" for the 32-bit CMT0 device included in r8a7795.
- "renesas,r8a7795-cmt1" for the 48-bit CMT1 device included in r8a7795.
- "renesas,r8a7795-cmt1" for the 48-bit CMT devices included in r8a7795.
- "renesas,r8a7796-cmt0" for the 32-bit CMT0 device included in r8a7796.
- "renesas,r8a7796-cmt1" for the 48-bit CMT1 device included in r8a7796.
- "renesas,r8a7796-cmt1" for the 48-bit CMT devices included in r8a7796.
- "renesas,r8a77965-cmt0" for the 32-bit CMT0 device included in r8a77965.
- "renesas,r8a77965-cmt1" for the 48-bit CMT1 device included in r8a77965.
- "renesas,r8a77965-cmt1" for the 48-bit CMT devices included in r8a77965.
- "renesas,r8a77970-cmt0" for the 32-bit CMT0 device included in r8a77970.
- "renesas,r8a77970-cmt1" for the 48-bit CMT1 device included in r8a77970.
- "renesas,r8a77970-cmt1" for the 48-bit CMT devices included in r8a77970.
- "renesas,r8a77980-cmt0" for the 32-bit CMT0 device included in r8a77980.
- "renesas,r8a77980-cmt1" for the 48-bit CMT1 device included in r8a77980.
- "renesas,r8a77980-cmt1" for the 48-bit CMT devices included in r8a77980.
- "renesas,r8a77990-cmt0" for the 32-bit CMT0 device included in r8a77990.
- "renesas,r8a77990-cmt1" for the 48-bit CMT1 device included in r8a77990.
- "renesas,r8a77990-cmt1" for the 48-bit CMT devices included in r8a77990.
- "renesas,r8a77995-cmt0" for the 32-bit CMT0 device included in r8a77995.
- "renesas,r8a77995-cmt1" for the 48-bit CMT devices included in r8a77995.
- "renesas,sh73a0-cmt0" for the 32-bit CMT0 device included in sh73a0.
- "renesas,sh73a0-cmt1" for the 48-bit CMT1 device included in sh73a0.
- "renesas,sh73a0-cmt2" for the 32-bit CMT2 device included in sh73a0.
- "renesas,sh73a0-cmt3" for the 32-bit CMT3 device included in sh73a0.
- "renesas,sh73a0-cmt4" for the 32-bit CMT4 device included in sh73a0.
- "renesas,rcar-gen2-cmt0" for 32-bit CMT0 devices included in R-Car Gen2
and RZ/G1.
@ -63,7 +69,7 @@ Required Properties:
listed above.
- "renesas,rcar-gen3-cmt0" for 32-bit CMT0 devices included in R-Car Gen3
and RZ/G2.
- "renesas,rcar-gen3-cmt1" for 48-bit CMT1 devices included in R-Car Gen3
- "renesas,rcar-gen3-cmt1" for 48-bit CMT devices included in R-Car Gen3
and RZ/G2.
These are fallbacks for R-Car Gen3 and RZ/G2 entries listed
above.

8
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@ -510,6 +510,14 @@
#pwm-cells = <2>;
status = "disabled";
};
system_counter: timer@306a0000 {
compatible = "nxp,sysctr-timer";
reg = <0x306a0000 0x20000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc_24m>;
clock-names = "per";
};
};
aips3: bus@30800000 {

8
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -635,6 +635,14 @@
#pwm-cells = <2>;
status = "disabled";
};
system_counter: timer@306a0000 {
compatible = "nxp,sysctr-timer";
reg = <0x306a0000 0x20000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc_25m>;
clock-names = "per";
};
};
bus@30800000 { /* AIPS3 */

2
drivers/clocksource/Kconfig
View File

@ -429,7 +429,7 @@ config ATMEL_ST
config ATMEL_TCB_CLKSRC
bool "Atmel TC Block timer driver" if COMPILE_TEST
depends on HAS_IOMEM
depends on ARM && HAS_IOMEM
select TIMER_OF if OF
help
Support for Timer Counter Blocks on Atmel SoCs.

4
drivers/clocksource/em_sti.c
View File

@ -291,10 +291,8 @@ static int em_sti_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, p);
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "failed to get irq\n");
if (irq < 0)
return irq;
}
/* map memory, let base point to the STI instance */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

2
drivers/clocksource/renesas-ostm.c
View File

@ -221,7 +221,7 @@ static int __init ostm_init(struct device_node *np)
}
rate = clk_get_rate(ostm_clk);
ostm->ticks_per_jiffy = (rate + HZ / 2) / HZ;
ostm->ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
/*
* First probed device will be used as system clocksource. Any

19
drivers/clocksource/sh_cmt.c
View File

@ -776,11 +776,8 @@ static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
int ret;
irq = platform_get_irq(ch->cmt->pdev, ch->index);
if (irq < 0) {
dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n",
ch->index);
if (irq < 0)
return irq;
}
ret = request_irq(irq, sh_cmt_interrupt,
IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
@ -921,12 +918,24 @@ static const struct platform_device_id sh_cmt_id_table[] = {
MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
{ .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] },
{
/* deprecated, preserved for backward compatibility */
.compatible = "renesas,cmt-48",
.data = &sh_cmt_info[SH_CMT_48BIT]
},
{
/* deprecated, preserved for backward compatibility */
.compatible = "renesas,cmt-48-gen2",
.data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
},
{
.compatible = "renesas,r8a7740-cmt1",
.data = &sh_cmt_info[SH_CMT_48BIT]
},
{
.compatible = "renesas,sh73a0-cmt1",
.data = &sh_cmt_info[SH_CMT_48BIT]
},
{
.compatible = "renesas,rcar-gen2-cmt0",
.data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]

5
drivers/clocksource/sh_tmu.c
View File

@ -462,11 +462,8 @@ static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,
ch->base = tmu->mapbase + 8 + ch->index * 12;
ch->irq = platform_get_irq(tmu->pdev, index);
if (ch->irq < 0) {
dev_err(&tmu->pdev->dev, "ch%u: failed to get irq\n",
ch->index);
if (ch->irq < 0)
return ch->irq;
}
ch->cs_enabled = false;
ch->enable_count = 0;

18
drivers/clocksource/timer-atmel-tcb.c
View File

@ -6,6 +6,7 @@
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/ioport.h>
#include <linux/io.h>
@ -125,6 +126,18 @@ static u64 notrace tc_sched_clock_read32(void)
return tc_get_cycles32(&clksrc);
}
static struct delay_timer tc_delay_timer;
static unsigned long tc_delay_timer_read(void)
{
return tc_get_cycles(&clksrc);
}
static unsigned long notrace tc_delay_timer_read32(void)
{
return tc_get_cycles32(&clksrc);
}
#ifdef CONFIG_GENERIC_CLOCKEVENTS
struct tc_clkevt_device {
@ -432,6 +445,7 @@ static int __init tcb_clksrc_init(struct device_node *node)
/* setup ony channel 0 */
tcb_setup_single_chan(&tc, best_divisor_idx);
tc_sched_clock = tc_sched_clock_read32;
tc_delay_timer.read_current_timer = tc_delay_timer_read32;
} else {
/* we have three clocks no matter what the
* underlying platform supports.
@ -444,6 +458,7 @@ static int __init tcb_clksrc_init(struct device_node *node)
/* setup both channel 0 & 1 */
tcb_setup_dual_chan(&tc, best_divisor_idx);
tc_sched_clock = tc_sched_clock_read;
tc_delay_timer.read_current_timer = tc_delay_timer_read;
}
/* and away we go! */
@ -458,6 +473,9 @@ static int __init tcb_clksrc_init(struct device_node *node)
sched_clock_register(tc_sched_clock, 32, divided_rate);
tc_delay_timer.freq = divided_rate;
register_current_timer_delay(&tc_delay_timer);
return 0;
err_unregister_clksrc:

5
drivers/clocksource/timer-imx-sysctr.c
View File

@ -20,6 +20,8 @@
#define SYS_CTR_EN 0x1
#define SYS_CTR_IRQ_MASK 0x2
#define SYS_CTR_CLK_DIV 0x3
static void __iomem *sys_ctr_base;
static u32 cmpcr;
@ -134,6 +136,9 @@ static int __init sysctr_timer_init(struct device_node *np)
if (ret)
return ret;
/* system counter clock is divided by 3 internally */
to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
sys_ctr_base = timer_of_base(&to_sysctr);
cmpcr = readl(sys_ctr_base + CMPCR);
cmpcr &= ~SYS_CTR_EN;

9
drivers/clocksource/timer-npcm7xx.c
View File

@ -32,7 +32,7 @@
#define NPCM7XX_Tx_INTEN BIT(29)
#define NPCM7XX_Tx_COUNTEN BIT(30)
#define NPCM7XX_Tx_ONESHOT 0x0
#define NPCM7XX_Tx_OPER GENMASK(27, 3)
#define NPCM7XX_Tx_OPER GENMASK(28, 27)
#define NPCM7XX_Tx_MIN_PRESCALE 0x1
#define NPCM7XX_Tx_TDR_MASK_BITS 24
#define NPCM7XX_Tx_MAX_CNT 0xFFFFFF
@ -84,8 +84,6 @@ static int npcm7xx_timer_oneshot(struct clock_event_device *evt)
val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
val &= ~NPCM7XX_Tx_OPER;
val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
val |= NPCM7XX_START_ONESHOT_Tx;
writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
@ -97,12 +95,11 @@ static int npcm7xx_timer_periodic(struct clock_event_device *evt)
struct timer_of *to = to_timer_of(evt);
u32 val;
writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
val &= ~NPCM7XX_Tx_OPER;
writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
val |= NPCM7XX_START_PERIODIC_Tx;
writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
return 0;

6
drivers/clocksource/timer-of.c
View File

@ -113,8 +113,10 @@ static __init int timer_of_clk_init(struct device_node *np,
of_clk->clk = of_clk->name ? of_clk_get_by_name(np, of_clk->name) :
of_clk_get(np, of_clk->index);
if (IS_ERR(of_clk->clk)) {
pr_err("Failed to get clock for %pOF\n", np);
return PTR_ERR(of_clk->clk);
ret = PTR_ERR(of_clk->clk);
if (ret != -EPROBE_DEFER)
pr_err("Failed to get clock for %pOF\n", np);
goto out;
}
ret = clk_prepare_enable(of_clk->clk);

4
drivers/clocksource/timer-probe.c
View File

@ -29,7 +29,9 @@ void __init timer_probe(void)
ret = init_func_ret(np);
if (ret) {
pr_err("Failed to initialize '%pOF': %d\n", np, ret);
if (ret != -EPROBE_DEFER)
pr_err("Failed to initialize '%pOF': %d\n", np,
ret);
continue;
}

4
drivers/clocksource/timer-sun4i.c
View File

@ -219,5 +219,9 @@ static int __init sun4i_timer_init(struct device_node *node)
}
TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
sun4i_timer_init);
TIMER_OF_DECLARE(sun8i_a23, "allwinner,sun8i-a23-timer",
sun4i_timer_init);
TIMER_OF_DECLARE(sun8i_v3s, "allwinner,sun8i-v3s-timer",
sun4i_timer_init);
TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
sun4i_timer_init);